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ZHCSE35 August 2015 DRV8305

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PHP|48
- MPQF051B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

PHP|48
- PPTD394

訂購信息

zhcse35_oa

7 Detailed Description

7.1 Overview

The DRV8305 is a 4.4-V to 45-V gate driver IC for three-phase motor driver applications. This device reduces external component count by integrating three half-bridge drivers, three current shunt amplifiers, and a LDO. The DRV8305 provides overcurrent, overtemperature, and undervoltage protection. Fault conditions are indicated by the nFAULT pin and specific fault indication can be read back from the SPI registers.

Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the external MOSFETs. Internal hand-shaking is used to prevent FET shoot through.

V_DS sensing of the external MOSFETs allows for the DRV8305 to detect overcurrent conditions and respond appropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.

There are three versions of DRV8305 with separate part numbers:

DRV8305N – VREG pin is used as input that supplies the reference for the CSA and SPI.
DRV83053 – VREG is a 3.3-V LDO output pin.
DRV83055 – VREG is a 5.0-V LDO output pin.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Three-Phase Gate Driver

The DRV8305 provides three half-bridge drivers, each driver is capable of driving two N-type MOSFETs, one for the high side and one for the low side.

Both the high side (GHX to SHX) and the low side (GLX to SLX) are implemented as floating gate drivers.

The gate driver uses a charge pump architecture which enables an extended voltage operating range to support a variety of application requirements.

7.3.2 Operating Modes

The DRV8305 can be operated in three modes, to support various commutation schemes.

Table 1 shows six independent PWM inputs with the truth table.

Table 1. 6-PWM Truth Table

INHX	INLX	GHX	GLX
1	1	L	L
1	0	H	L
0	1	L	H
0	0	L	L

Three independent high-side PWM inputs (low-side complimentary PWMs generated internally).

In this mode all activity on INLA, INLB and INLC is ignored.

Table 2. 3-PWM Truth Table

INHX	INLX	GHX	GLX
1	X	H	L
0	X	L	H

One single PWM that uses internally stored 6-step block commutation tables. In this mode of operation, DRV8305 can be operated using a single PWM sourced from a low cost microcontroller. The PWM is applied on pin PWM_IN (INHA) from the microcontroller along with three GPIO pins PHC_0 (INLA), PHC_1 (INHB), PHC_2 (INLB) that serve to set the bits of a three bit register. The PWM may be operated from 0-100% duty cycle. The three bit register is used to select the state of each of the phases for a total of eight states including an align and stop state. The 1-PWM mode tables will use all the applicable settings from the control registers as set up by the user.

An additional and optional GPIO (INHC) can be used to facilitate the insertion of dwell states or phase current overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve motion through the reduction of abrupt current direction changes when switching between states. INHC must be high when the states are changed and the dwell state will exist until INHC is taken low. If the dwell states are not being used, the INHC pin can be simply tied low.

In this mode all activity on INLC is always ignored.

The commutation tables ( Table 3 and Table 4) may be selected through the appropriate SPI register.

Table 3. 1-PWM Active Freewheeling

	INLA : INHB : INLB : INHC	AH	AL	BH	BL	CH	CL
AB	0110	PWM	!PWM	LOW	HIGH	LOW	LOW
AB_CB	0101	PWM	!PWM	LOW	HIGH	PWM	!PWM
CB	0100	LOW	LOW	LOW	HIGH	PWM	!PWM
CB_CA	1101	LOW	HIGH	LOW	HIGH	PWM	!PWM
CA	1100	LOW	HIGH	LOW	LOW	PWM	!PWM
CA_BA	1001	LOW	HIGH	PWM	!PWM	PWM	!PWM
BA	1000	LOW	HIGH	PWM	!PWM	LOW	LOW
BA_BC	1011	LOW	HIGH	PWM	!PWM	LOW	HIGH
BC	1010	LOW	LOW	PWM	!PWM	LOW	HIGH
BC_AC	0011	PWM	!PWM	PWM	!PWM	LOW	HIGH
AC	0010	PWM	!PWM	LOW	LOW	LOW	HIGH
AC_AB	0111	PWM	!PWM	LOW	HIGH	LOW	HIGH
Align	1110	PWM	!PWM	LOW	HIGH	LOW	HIGH
Stop	0000	LOW	LOW	LOW	LOW	LOW	LOW

Table 4. 1-PWM Diode Freewheeling

	INLA : INHB : INLB : INHC	AH	AL	BH	BL	CH	CL
AB	0110	PWM	LOW	LOW	HIGH	LOW	LOW
AB_CB	0101	PWM	LOW	LOW	HIGH	PWM	LOW
CB	0100	LOW	LOW	LOW	HIGH	PWM	LOW
CB_CA	1101	LOW	HIGH	LOW	HIGH	PWM	LOW
CA	1100	LOW	HIGH	LOW	LOW	PWM	LOW
CA_BA	1001	LOW	HIGH	PWM	LOW	PWM	LOW
BA	1000	LOW	HIGH	PWM	LOW	LOW	LOW
BA_BC	1011	LOW	HIGH	PWM	LOW	LOW	HIGH
BC	1010	LOW	LOW	PWM	LOW	LOW	HIGH
BC_AC	0011	PWM	LOW	PWM	LOW	LOW	HIGH
AC	0010	PWM	LOW	LOW	LOW	LOW	HIGH
AC_AB	0111	PWM	LOW	LOW	HIGH	LOW	HIGH
Align	1110	PWM	LOW	LOW	HIGH	LOW	HIGH
Stop	0000	LOW	LOW	LOW	LOW	LOW	LOW

7.3.3 Charge Pump

A regulated triple charge pump scheme is used to create sufficient V_GS to drive standard FETs under low voltage operation.

The high-side FETs are directly driven by the tripler charge pump output while the low-side FETs are driven by a voltage that is internally regulated but derived from the tripler charge pump. This allows both the high side and low side to maintain sufficient V_GS through low voltage transients. This topology also supports 100% duty cycle operation.

Between 4.4 to 18 V the charge pump regulates the voltage in tripler mode; beyond 4.4 to 18 V, it switches over to doubler mode until the operating max voltage. The charge pump is monitored for undervoltage and overvoltage conditions to prevent underdriven or overdriven FET conditions.

7.3.4 Gate Driver Architecture

The DRV8305 gate driver is a complimentary push-pull topology for both the high-side and the low-side drivers. The peak currents for the drivers are adjustable; their benefits are described in detail in the Slew Rate/Slope Control section.

The gate driver is implemented as constant current sources for up to 80 mA (sink)/70 mA (source) currents in order to maintain the accuracy required for precise slew rate control. Beyond that, resistors are switched to create the desired settings up to 1.25 A (sink)/1 A (source).

7.3.5 IDRIVE/TDRIVE

The DRV8305 gate driver has an integrated state machine (TDRIVE/IDRIVE scheme) to protect against high current events on the outputs (shorts or inadvertent clamp activation) and also dV/dt turn on due to switching on the phase nodes.

When changing the state of the gate driver, the peak current (source or sink, IDRIVE) is applied for a fixed period of time (TDRIVE) until the gate capacitances are charged or discharged completely. After this time has expired, a fixed current source of I_HOLD is used to hold the gate at the desired state (pulled up or pulled down).

Figure 7. TDRIVE/IDRIVE Waveforms

This fixed TDRIVE time ensures that under abnormal circumstances like a short on the FET gate, or the inadvertent turning on of a FET V_GS clamp, the high peak current through the DRV8305 gate drivers is limited to the energy of the peak current during TDRIVE. Limiting this energy helps to prevent the gate driver from damage.

Select a TDRIVE time that is longer than the time needed to charge or discharge the gate capacitances. IDRIVE and TDRIVE are selected based on the size of external FETs used and the desired rise and fall times. These registers must be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and TDRIVE are too low for a given FET, then the FET may not turn on completely. TI suggests to adjust these values in-system with the required external FETs to determine the best possible setting for any application.

Note that TDRIVE will not increase the PWM time and will simply terminate if a PWM command is received while it is active. A good starting point is to select a TDRIVE that is about 2× longer than the external FET switching rise (turn ON) and fall (turn OFF) times.

The IDRIVE/TDRIVE state machine protects against dV/dt turn on of a FET due to switching of the phase nodes. A strong pulldown current source of value I_PULLDOWN is switched on between (GHX to SHX) or (GLX to SLX), every time an opposing FET is commanded to turn on.

7.3.6 Slew Rate/Slope Control

Control of the FET VDS rise and fall times during the Miller region of the FET is one of the most important parameters for optimizing emitted radiations and power. The rise and fall times also influence the energy and duration of the diode recovery inductive spikes and also dV/dt turn on of the LS FET.

The ability of a driver to control the rise and fall times across the entire range of gate drive temperature, voltage, and process variation is essential to design robust systems. The key control knob is the ability to turn on and turn off the external FET with the least amount of variation.

The DRV8305 uses temperature compensated constant current sources up to 80-mA (sink) and 70-mA (source) current. The current source architecture helps eliminate the temperature, process, and load-dependent variation associated with internal and external series limiting resistors.

For higher currents, internal series resistors are used to minimize the power losses associated with mirroring such large currents.

The 12 settings that are available on the DRV8305 allow the user to optimize the system using only SPI commands. This flexibility allows the system designer to tune the performance of the driver for different operating conditions through software alone.

The slew rate settings may be set separately for source and sink values and can also be set separately for the high-side FETs (the high sides of all three phases share the same setting) and the low-side FETs (the low sides of all three phases share the same settings)

7.3.7 Current Shunt Amplifiers

The DRV8305 includes three high performance low-side current shunt amplifiers for accurate current measurement. The current amplifiers provide output bias up to 2.5 V to support bidirectional current sensing.

Current shunt amplifier has following features:

Each of the three current sense amplifiers can be programmed and calibrated independently.
The independent current shunt amplifiers may be used either for sensing current through individual phase shunt resistors or the total current delivered to the motor through a single shunt resistor.
Programmable gain: four gain settings through SPI command
Internally or externally provided reference voltage to set output bias for amplifiers. Reference voltage is internally sourced from DRV8305 voltage regulator VREG, if also used to power microcontroller. It can alternatively be applied externally on the VREG pin.
Programmable output bias scaling. The scaling factor k can be programmed through SPI to be equal to, half or a fourth of the reference voltage.
Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any rising or falling edge (any of the outputs) of the internal gate driver gate signals. The blanking time is applied to all three current sense amplifiers equally. In case the current sense amplifiers are already being blanked when another gate driver rising or falling edge is seen, the blanking interval will be restarted at the edge.

Note that the blanking time options do not include delay from internal amplifier loading or delays from the trace or component loads on the amplifier output. The programmable blanking time may be overridden to have no delay (default value).

Minimize DC offset and drift through temperature with DC calibrating through SPI command. When DC calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating can be done at anytime, even when the FET is switching because the load is disconnected. For best result, perform the DC calibrating during switching off period when no load is present to reduce the potential noise impact to the amplifier.

The output of current shunt amplifier can be calculated as:

Equation 1. DRV8305 eq_01_lvscx2.gif

where

VREF is the reference voltage.
G is the gain of the amplifier.
k = 2, or 4
SNx and SPx are the inputs of channel x. SPx should connect to resistor ground for the best common mode rejection.

Figure 8 shows current amplifier simplified block diagram.

Figure 8. Current Shunt Amplifier Simplified Block Diagram

7.3.8 Internal Regulators (DVDD and AVDD)

The DRV8305 has two internal regulators, DVDD and AVDD, that power internal circuits. These regulators cannot be used to drive external loads and may not be supplied externally.

DVDD is the voltage regulator for the internal logic circuits and is maintained at a value of about 3.3 V through the entire operating range of the device. DVDD is derived from the PVDD supply.

AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the current sense amplifiers. AVDD is derived from the PVDD voltage supply.

Because the allowed operating range of the device permits operation below the nominal value of AVDD, this regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout region, the AVDD will simply track the PVDD voltage minus a voltage drop.

If the device is expected to operate within the dropout region, take care while selecting current sense amplifier components and settings to accommodate this reduced voltage rail.

7.3.9 Voltage Regulator Output for Driving External Loads (VREG)

The DRV8305 integrates an LDO voltage regulator (VREG) that is dedicated for driving external loads like an MCU directly. The two versions of the device provide different voltages: DRV83053 provides 3.3 V, DRV83055 provides 5.0 V. Because the user can supply microcontroller and other system power from the DRV8305, the user does not need to add an external regulator IC for system power.

The DRV8305 voltage regulator is standalone, uncommitted, and is not used internally.

The DRV8305 voltage regulator also features a PWRGD pin to protect against brownouts on externally driven devices. The PWRGD pin is often tied to a reset pin on a microcontroller to ensure that the microcontroller is always reset when the voltage is outside of its recommended operation area.

When the voltage output of the LDO drops or exceeds the set threshold (programmable).

The PWRGD pin will go low for a period of 64 µs.
After the 64-µs period has expired, the LDO voltage will be checked and PWRGD will be held low until the LDO voltage has recovered.

The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and output voltage (VREG).

7.3.10 Protection Features

Fault / Warning Classes and Recovery summarizes the protection features, fault responses, and recovery sequences.

7.3.10.1 Fault and Protection Handling

The DRV8305 handles fault (latched fault) and warnings (unlatched faults) separately. Both latched and unlatched faults are reported in status registers and can be read through SPI.

A latched nFAULT pin indicates an error event has occurred that has caused part of the gate driver to shut down and force outputs to a safe state (external FETs in high impedance).
- A latched fault is indicated by the nFAULT pin going low (and staying low) and reporting the details of the fault in the status registers (0x02 and 0x03). The appropriate recovery sequence must be performed in order to reset the latched fault. In addition, the register (0x01) contains a single status bit if any latched faults are detected.
- The nFAULT pin will stay low until the appropriate recovery sequence is performed.

TI recommends to inspect the system and board when a latched nFAULT faults occurs.

An unlatched warning on nFAULT pin indicates that an event that requires a warning to be communicated has occurred.
- An unlatched fault is indicated by the nFAULT pin going low for a period of 64 µs, reporting the warning and then recovering back high for a period of 64 µs before reporting any subsequent errors.
- When a warning has been read by SPI through the warning register (0x01), that same warning will not be reported through nFAULT again unless that warning or condition passes and then reoccurs.
- In case another warning or warnings are received during the 64-µs period but after the warning register has been read, then after the expiration of 64 µs, the nFAULT pin will go high for another 64 µs and then report those warning or warnings by going low for another 64 µs.
- If a latched fault occurs during a period where nFAULT is low, then the nFAULT pin will stay low.

Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.

7.3.10.2 Shoothrough Protection

DRV8305 integrates analog and digital monitors to prevent shoot-through in the external FETs.

An Internal handshake through analog comparators is performed between high-side and low-side FETs during switching transition.
A minimum dead time (digital) of 40 ns is always inserted after a successful handshake. This digital dead-time is programmable and is in addition to the time taken for the handshake.

7.3.10.3 VDS Sensing – External FET Protection and Reporting (OC Event)

To protect the external FETs from damage due to high currents, V_DS sensing circuitry is implemented in the DRV8305.

The V_DS sensing is implemented for both the high-side and low-side MOSFET through these pins:

High-side MOSFET: V_DS measured between VDRAIN and SHX pins
Low-side MOSFET: V_DS measured between SHX and SLX pins

Based on R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be calculated, which when exceeded, triggers the V_DS protection feature.

This voltage threshold level is programmable through SPI command and may be programmed during operation if needed.

The V_DS protection logic also has an adjustable blanking time and deglitch time to prevent false trips.

V_DS blanking time (t_BLANK): This time is inserted digitally and is programmable. The t_BLANK time is a delay inserted at each output after that particular output has been commanded to turn ON. During t_BLANK time, the VDS comparators are not being monitored in order to prevent false trips when the FETs first turn ON.

V_DS deglitch time (t_VDS): This time is inserted digitally and is programmable. The t_VDS time is a delay inserted after the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has occurred.

Note that the dead time and blanking time are overlapping counters as shown in Figure 9

Figure 9. VDS Protection Timing

Three overcurrent responses are possible depending on the configuration option selected through SPI.

V_DS event latch shutdown mode

When a VDS event occurs, device will pull all outputs low in order to take all six external FETs into high-impedance mode. The Fault will be reported on nFAULT and details of the FET that reported the fault can be read back through SPI.

V_DS event Reporting only mode

In this mode, VDS event will be reported on the nFAULT pin and the SPI register. Gate drivers will continue to operate.

V_DS event disable mode

Device ignores all the V_DS event detections and does not report them.

7.3.10.4 Low-Side Source Monitoring (SNS_OCP)

The DRV8305 monitors the voltage on the SLX pins for high-current events like phase shorts that may cause the voltage on those pins to exceed 2 V. The device will put the FETs into a high-impedance state to avoid damage.

7.3.11 Undervoltage Reporting and Undervoltage Lockout (UVLO) Protection

The DRV8305 implements appropriate undervoltage responses in order to protect the system. Fault / Warning Classes and Recovery lists the details of the monitors and their response and recovery sequences.

Under-voltage is monitored on PVDD, AVDD, VCPH, and VCP_LSD.

The UVLO protection fault may be completely disabled for the PVDD undervoltage condition using a SPI register command. In this case, the fault is still reported in the register.

The UVLO protection may never be completely disabled for the VCPH or VCP_LSD in OPERATING mode because this may indicate a short condition that could damage the DRV8305.

7.3.11.1 Battery Overvoltage Protection (PVDD_OV)

The DRV8305 implements appropriate overvoltage responses in order to protect the system.

PVDD is monitored for overvoltage conditions. If the overvoltage threshold is tripped, a warning is issued and the event is reported in the status registers. The device takes no action.

7.3.11.2 Charge Pump Overvoltage Protection (VCPH_OV/VCP_LSD_OV)

If VCPH or VCP_LSD exceed the overvoltage threshold due to potential issue related to the charge pumps (for example, short of external charge pump capacitor or charge pump, an overvoltage fault is triggered).

7.3.11.3 Overtemperature (OT) Warning and Protection

A multi-level temperature detection circuit is implemented:

Flag Level 1: Level 1 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
Flag Level 2: Level 2 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
Flag Level 3: Level 3 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
Flag Level 4: Level 4 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
Warning Level: Overtemperature warning only. Warning is reported on nFAULT for 64 µs and can be read through SPI.
Fault Level: Overtemperature fault and latched shut down of gate driver and charge pump Fault will be reported to nFAULT pin.

SPI operation is still available and register settings will be retained in the device during OTSD operation as long as PVDD is still within defined operation range.

The details of the fault will be reported into a register that can be read back through SPI.

7.3.11.4 dV/dt Protection

The DRV8305 gate driver implements a strong pulldown scheme for preventing dV/dt turn on of external FETs. After a FET has been turned off using the selected sink slew rate setting, the internal state machine will turn on a stronger pulldown if it senses that the opposite FET on that phase has been commanded to turn on. This allows the systems designer to decouple the optimum slew rate setting selection for EMI and power from the pull down required to prevent dV/dt turn on.

7.3.11.5 VGS Protection

The DRV8305 gate driver uses a multilevel level protection scheme to protect the external FET from VGS voltages that may damage the gate of the external FET.

The device integrates VGS clamps inside the gate driver that will turn on when the GHX voltage exceeds SHX voltage by a value that could be damaging to the FETs. If the voltage continues to rise, in spite of the clamps turning on, the TDRIVE architecture ensures that the energy through the clamps is limited. If the high VGS voltage is due to an abnormal condition on the charge pump, the charge pump overvoltage fault will trip in order to protect the FETs from damage.

7.3.11.6 Gate Driver Faults

The DRV8305 protects against abnormal short to battery or short to ground conditions on the gate driver outputs that could result in an incorrect state of the gate driver outputs. The gate driver integrates VGS comparators that check the status of the gate driver output against the commanded PWM signal to ensure that they match. This comparison occurs shortly after the expiration of the TDRIVE time. If the comparison indicates a mismatch, a gate driver fault is indicated.

7.3.11.7 Reverse Battery Protection

The VCPH pin on the DRV8305 is designed to be able to supply an external load of up to 10 mA. This feature allows implementation of an external reverse battery protection scheme using a MOS and a BJT. The MOS gate can be driven through VCP through a current limiting resistor to limit the current drawn from VCP. The current limit resistor must be sized not to exceed the maximum external load on VCPH.

The VDRAIN pin (sense) may also be protected against negative transients on it by use of a current limiting resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin.

Figure 10. Typical Scheme for Reverse Battery Protection Using VCPH

7.3.11.8 MCU Watchdog

An MCU watchdog function may be enabled to ensure that the external controller that is instructing the DRV8305 is active and not in an unknown state.

SPI Watchdog must be enabled by writing a 1 to the WD_EN bit through SPI (default is disabled = 0).

When the SPI watchdog is enabled, an internal timer starts to countdown to an interval set by WD_dly bit.

To reset the watchdog, the address 0x01 (Status register) must be read by the microcontroller within the interval set by the register WD_dly.

If the timer is allowed to expire without the address 0x01 being read, the WD fault will get enabled.

Response to this fault is as follows:

A Latched + PWRGD fault occurs on the DRV8305 and gate drivers are put into a safe state. The appropriate recovery sequence must be performed.
PWRGD pin is taken low for 64 µs and then back high in order to reset the microcontroller.
nFAULT is asserted
WD_EN bit is cleared
Report that the watchdog had expired through SPI bit WD_FAULT
TI recommends that if the watchdog function is being used, the MCU software routine reads the status registers as part of its recovery or power-up routine in order to know whether a WD_FAULT had previously occurred.

Note that the fault results in clearing of the WD_EN bit and it will have to be set again to resume watchdog functionality.

7.3.12 Pin Control Functions

7.3.12.1 EN_GATE

EN_GATE low is used to put the gate driver into standby mode. Note that EN_GATE has no effect on the LDO voltage regulator. When EN_GATE is low, the device will always put the MOSFET output stage to high impedance as long as PVDD is still present. EN_GATE is also used to reset the IC.

It is not possible to enter SLEEP mode without taking EN_GATE low and entering STANDBY mode first.

TI recommends to take EN_GATE for at least greater than 25 µs when it is asserted low to go into standby mode.

7.3.12.2 SPI Pins

SDO pin has to be tri-state, so a data bus line can be connected to multiple SPI slave devices. SCS pin is active low. When SCS is high, SDO is at high-impendence mode.

Ensure that SDO pin is always configured in the system as an output from DRV8305.

SDO pin must never be driven to ensure correct operation of DRV8305. SDO is referrenced to the VREG voltage.

Table 5. Fault / Warning Device Status

CONDITION	CLASS	OUTPUTS PD – PULL DOWN O – OPERATING	CHARGE PUMP O – OPERATING SD – SHUTDOWN	AVDD / DVDD O – OPERATING SD – SHUTDOWN	VOLTAGE REGULATOR O – OPERATING SD – SHUTDOWN
PVDD undervoltage (V_{PVDD_UVLO1}) falling	None	PD	SD	SD	SD
PVDD undervoltage (V_{PVDD_UVLO2}) falling	Latched	PD	SD	O	O
PVDD undervoltage (V_{PVDD_UVFL}) falling	Warning	O	O	O	O
PVDD overvoltage (V_{PVDD_OVFL}) rising	Warning	O	O	O	O
Charge pump undervoltage (VVCPH_UVFL) falling	Warning	O	O	O	O
Charge pump undervoltage (V_{VCPH_UVLO} / V_{VCP_LSD_UVLO})	Latched	PD	SD	O	O
Charge pump overvoltage (V_{VCPH_OVLO}, V_{VCPH_OVLO_ABS})	Latched	PD	SD	O	O
AVDD undervoltage	Latched	PD	SD	SD	O
TEMP FLAG 1/2/3/4	Real time	O	O	O	O
OT warning (OTW)	Warning	O	O	O	O
OT shutdown (OTS)	Latched	PD	SD	O	O
VDS event – latch mode (FETxx_VDS)	Latched	PD	O	O	O
VDS event – report mode (FETxx_VDS)	Report only	O	O	O	O
VDS event – disable mode (FETxx_VDS)	Not reported	O	O	O	O
SNS OCP	Latched	PD	O	O	O
Gate driver fault VGS event	Latched	PD	SD	O	O
MCU watchdog	Latched + PWRGD	PD	O	O	O
VREG_UV	Latched + PWRGD	PD	O	O	O

7.3.13 Fault / Warning Classes and Recovery

7.3.13.1 Reg 09h CLR_FLTS

When CLR_FLTS bit is set to 1, all expired faults (latch/warn) will be cleared from the SPI status register. Also, the nFAULT pin will be released on the event of an expired Latched fault. CLR_FLTS provides a software reset option to DRV8305. The effect on nFAULT pin and SPI status registers is the same as pulling EN_GATE pin low and taking it HIGH.

CLR_FLTS bit self clears to 0 after SPI status register is reset and nFAULT pin is released.

Table 6. Fault / Warning Reporting and Handling

CLASS	nFAULT	PWRGD	SPI REPORT	DEVICE RECOVERY SEQUENCE	SPI REPORT RECOVERY
Latched	Low	No action	Yes	Toggle EN_GATE (Faults clear on rising edge of EN_GATE) OR Write Reg 09h CLR_FLTS bit set 1	Bit clears only on successful fault recovery
Warning	Toggles with 64-µs period	No action	Yes	Read SPI status register 0x01 to acknowledge warning (otherwise nFAULT will continue to toggle)	Bit clears on register read only if condition has passed
Report only (VDS mode)	Toggles with 64-µs period	No action	Yes	Read SPI status register 0x01 to acknowledge warning (otherwise nFAULT will continue to toggle)	Bit clears on register read only if condition has passed
Real time	No action	No action	Yes	Read SPI register to capture real time status	Bit clears after condition has passed
Not reported	No action	No action	No	None	None
Latched + PWRGD	Low	Low for minimum of 64 µs	Yes	Toggle EN_GATE (Faults clear on rising edge of EN_GATE) OR Write Reg 09h CLR_FLTS bit set 1	Bit clears only on successful fault recovery

7.4 Device Functional Modes

7.4.1 Power-Up and Operating States Hardware Configuration for VREG/VREF

Hardware configuration is not required. Voltage regulator voltage (3.3 or 5 V or disabled) is based on orderable part number.

7.4.1.1 POWER Up

During power-up, all internal circuits are enabled. The VREG will also be enabled based on the hardware configuration (see Voltage Regulator Control (address = 0xB) section). All gate drive outputs are held low and the nFAULT pin is taken low by the IC while power up is being executed.

7.4.1.2 STANDBY State

After the startup sequence is completed and the PVDD voltage is above V_{PVDD_UVLO2}, the DRV8305 will indicate successful and fault-free power up of all circuits by releasing the nFAULT pin.

The device will also enter STANDBY state any time that EN_GATE is taken low or a latched fault occurs.

Gate driver always has control of the power FETs even in STANDBY state.

TI recommends to set up the device control registers through SPI in the STANDBY state.

7.4.1.3 OPERATING State

Normal operation of the gate driver and current shunt amplifiers can be initiated by taking EN_GATE from a low state to a high state. In this state the charge pump is powered up and the driver is ready for operation.

7.4.1.4 SLEEP State

The SLEEP state is invoked by issuing a SLEEP command through SPI. After the SLEEP command is received, the VREG and the gate driver safely power down internally after a programmable delay.

The DRV8305 can then only be enabled through the WAKE pin which is a high-voltage-tolerant input pin.

For the DRV8305 to be brought out of SLEEP, the WAKE pin must be at a voltage greater than 3 V. This allows the WAKE to be driven, for example, directly by the battery through a switch, through the inhibit pin (INH) on standard LIN interface or through standard digital logic. The WAKE pin will only react to a wake-up command if PVDD > V_{PVDD_UVLO2}.

After the DRV8305 is out of SLEEP mode, all activity on the WAKE pin is ignored.

SLEEP state erases the values in the SPI control registers. TI does not recommend to write through SPI in SLEEP state.

7.5 Programming

7.5.1 SPI Communication

7.5.1.1 SPI

SPI is used to set device configuration, operating parameters, and read out diagnostic information. The DRV8305 SPI operates in slave mode.

The SPI input data (SDI) word consists of a 16-bit word with 11-bit data and 5-bit (MSB) command. The SPI output data (SDO) word consists of 11-bit register data. (The first 5 bits (MSB) are to be ignored.)

A valid frame must meet following conditions:

Clock must be low when nSCS goes low.
It should have 16 full clock cycles.
Clock must be low when nSCS goes high.

Data is always shifted out on the rising edge of the clock in the same frame following the 5-bit MSB.

Data is always sampled on the falling edge of the clock in the same frame following the 5-bit MSB.

When SCS is asserted high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a high-impedance state. When SCS transitions from HIGH to LOW, SDO is enabled and the SPI response word loads into the shift register based on 5-bit command.

The SCLK pin must be low when SCS transitions low. While SCS is low, at each rising edge of the clock, the response bit is serially shifted out on the SDO pin with MSB shifted out first.

While SCS is low, at each falling edge of the clock, the new control bit is sampled on the SDI pin. The SPI command bits are decoded to determine the register address and access type (read or write). The MSB will be shifted in first. If the word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error and the data will not be written into the destination address. If it is a write command, the data will be ignored.

For a write command, the existing data in the register being written to is shifted out on SDO following the 5-bit MSB.

SCS should be taken high for at least 500 ns between frames.

7.5.1.2 SPI Format

SPI input data control word is 16-bit long, consisting of:

1 read or write bit W [15]
4 address bits A [14:11]
11 data bits D [10:0]

SPI output data response word is 11-bit long (first 5 bits are ignored) and its content is the content of the register being accessed

For a Write transaction: The response word is the data currently in the register being written to.

For a Read Command: The response word is the data currently in the register being read.

Table 7. SPI Input Data Control Word Format

	R/W	ADDRESS				DATA
Word Bit	B15	B14	B13	B12	B11	B10	B9	B8	B7	B6	B5	B4	B3	B2	B1	B0
Command	W0	A3	A2	A1	A0	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

Table 8. SPI Output Data Response Word Format

	DATA
Word Bit	B15	B14	B13	B12	B11	B10	B9	B8	B7	B6	B5	B4	B3	B2	B1	B0
Command	X	X	X	X	X	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

7.6 Register Maps

Table 9. Register Map

ADDRESS	NAME	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
0x1	Warning & Watch Dog	FAULT	Reserved	TEMP_FLAG4	PVDD_UVFL	PVDD_OVFL	VDS_STATUS	VCPH_UVFL	TEMP_FLAG1	TEMP_FLAG2	TEMP_FLAG3	OTW
0x2	OV/VDS Faults	FETHA_VDS	FETLA_VDS	FETHB_VDS	FETLB_VDS	FETHC_VDS	FETLC_VDS	Reserved	Reserved	SNS_C_OCP	SNS_B_OCP	SNS_A_OCP
0x3	IC Faults	PVDD_UVLO2	WD_FAULT	OTS	Reserved	VREG_UV	AVDD_UVLO	VCP_LSD_UVLO	Reserved	VCPH_UVLO	VCPH_OVLO	VCPH_OVLO_ABS
0x4	Gate drvier VGS Faults	FETHA_VGS	FETLA_VGS	FETHB_VGS	FETLB_VGS	FETHC_VGS	FETLC_VGS	Reserved	Reserved	Reserved	Reserved	Reserved
0x5	HS Gate Driver Control	Reserved	TDRIVEN[1]	TDRIVEN[0]	IDRIVEN_HS[3]	IDRIVEN_HS[2]	IDRIVEN_HS[1]	IDRIVEN_HS[0]	IDRIVEP_HS[3]	IDRIVEP_HS[2]	IDRIVEP_HS[1]	IDRIVEP_HS[0]
0x6	LS Gate Driver Control	Reserved	TDRIVEP[1]	TDRIVE[0]	IDRIVEN_LS[3]	IDRIVEN_LS[2]	IDRIVEN_LS[1]	IDRIVEN_LS[0]	IDRIVEP_LS[3]	IDRIVEP_LS[2]	IDRIVEP_LS[1]	IDRIVEP_LS[0]
0x7	Gate Drive Control	Reserved	COMM_OPTION	PWM_MODE[1]	PWM_MODE[0]	DEAD_TIME[2]	DEAD_TIME[1]	DEAD_TIME[0]	TBLANK[1]	TBLANK[0]	TVDS[1]	TVDS[0]
0x8	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
0x9	IC Operation	FLIP_OTS	DISABLE VPVDD_UVLO2	DIS_GDRV FAULT	EN_SNS_CLAMP	WD_DLY[1]	WD_DLY[0]	DIS_SNS_OCP	WD_EN	SLEEP	CLR_FLTS	SET_VCPH_UV
0xA	Shunt Amplifier Control	DC_CAL_CH3	DC_CAL_CH2	DC_CAL_CH1	CS_BLANK[1]	CS_BLANK[0]	GAIN_CS3[1]	GAIN_CS3[0]	GAIN_CS2[1]	GAIN_CS2[0]	GAIN_CS1[1]	GAIN_CS1[0]
0xB	Voltage Regulator Control	Reserved	VREF_SCALE[1]	VREF_SCALE[0]	Reserved	Reserved	Reserved	SLEEP_DLY[1]	SLEEP_DLY[0]	DIS_VREG_PWRGD	VREG_UV_LEVEL[1]	VREG_UV_LEVEL[0]
0xC	VDS Sense Control	Reserved	Reserved	Reserved	VDS_LEVEL[4]	VDS_LEVEL[3]	VDS_LEVEL[2]	VDS_LEVEL[1]	VDS_LEVEL[0]	VDS_MODE[2]	VDS_MODE[1]	VDS_MODE[0]

7.6.1 Read / Write Bit

The MSB bit of SDI word (W0) is read/write bit. When W0 = 0, input data is a write command; when W0 = 1, input data is a read command, and the register value will send out on the same word cycle from SDO from D10 to D0.

7.6.2 Status Registers

Status registers are used to report warning, fault conditions and provide a means to prevent timing out of the watchdog timer. Status registers are read only registers.

7.6.3 0x1 Warning and Watchdog Reset

Table 10. Warning and Watchdog Reset Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R	FAULT	0x0	0 - Warning, 1 - Latched fault
9	R	Reserved	0x0
8	R	TEMP_Flag4	0x0	Temperature flag setting for about 175°C
7	R	PVDD_UVFL	0x0	PVDD undervoltage flag warning
6	R	PVDD_OVFL	0x0	PVDD overvoltage flag warning
5	R	VDS_STATUS	0x0	Real time or of all VDS sensors (0x2[D10:5])
4	R	VCHP_UVFL	0x0	Charge pump undervoltage flag warning
3	R	TEMP_Flag1	0x0	Temperature flag setting for about 105°C
2	R	TEMP_Flag2	0x0	Temperature flag setting for about 125°C
1	R	TEMP_Flag3	0x0	Temperature flag setting for about 135°C
0	R	OTW	0x0	Overtemperature warning

7.6.4 0x2 OV/VDS Faults

Table 11. OV/VDS Faults Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R	FETHA_VDS	0x0	VDS monitor fault for high-side FET A
9	R	FETLA_VDS	0x0	VDS monitor fault for low-side FET A
8	R	FETHB_VDS	0x0	VDS monitor fault for high-side FET B
7	R	FETLB_VDS	0x0	VDS monitor fault for low-side FET B
6	R	FETHC_VDS	0x0	VDS monitor fault for high-side FET C
5	R	FETLC_VDS	0x0	VDS monitor fault for low-side FET C
4:3	R	Reserved	0x0
2	R	SNS_C_OCP	0x0	Sense C overcurrent protection flag
1	R	SNS_B_OCP	0x0	Sense B overcurrent protection flag
0	R	SNS_A_OCP	0x0	Sense A overcurrent protection flag

7.6.5 0x3 IC Faults

Table 12. IC Faults Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R	PVDD_UVLO2	0x0	PVDD undervoltage 2 fault
9	R	WD_FAULT	0x0	Watchdog fault
8	R	OTS	0x0	Overtemperature fault
7	R	Reserved	0x0
6	R	VREG_UV	0x0	VREG undervoltage fault
5	R	AVDD_UVLO	0x0	AVDD undervoltage fault
4	R	VCP_LSD_UVLO	0x0	Charge pump low-side gate driver fault
3	R	Reserved	0x0
2	R	VCPH_UVLO	0x0	Charge pump high-side undervoltage 2 fault
1	R	VCPH_OVLO	0x0	Charge pump high-side overvoltage fault
0	R	VCPH_OVLO_ABS	0x0	Charge pump high-side overvoltage ABS fault

7.6.6 0x4 Gate Driver VGS Faults

Table 13. Gate Driver VGS Faults Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R	FETHA_VGS	0x0	VGS monitor fault for high-side FET A
9	R	FETLA_VGS	0x0	VGS monitor fault for low-side FET A
8	R	FETHB_VGS	0x0	VGS monitor fault for high-side FET B
7	R	FETLB_VGS	0x0	VGS monitor fault for low-side FET B
6	R	FETHC_VGS	0x0	VGS monitor fault for high-side FET C
5	R	FETLC_VGS	0x0	VGS monitor fault for low-side FET C
4:0	R	Reserved	0x0

7.6.7 Control Registers

Control registers are used to set the user parameter for DRV8305. The default values are shown in bold.

Control registers may be read and do not clear on read or EN_GATE resets
Control registers are cleared to default values on power up
Control registers are cleared to default values when the device enters SLEEP mode

7.6.7.1 HS Gate Driver Control (address = 0x5)

Table 14. HS Gate Driver Control Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R/W	Reserved	0x0
9:8	R/W	TDRIVEN	0x3	High-side gate driver peak source time b'00 - 250 ns b'01 - 500 ns b'10 - 1000 ns b'11 - 2000 ns
7:4	R/W	IDRIVEN_HS	0x4	High-side gate driver peak sink current
7:4	R/W	IDRIVEN_HS	0x4	b'0000 - 20 mA b'0100 - 60 mA b'1000 - 0.50 A b'1100 - 60 mA	b'0001 - 30 mA b'0101 - 70 mA b'1001 - 0.75 A b'1101 - 60 mA	b'0010 - 40 mA b'0110 - 80 mA b'1010 - 1.00 A b'1110 - 60 mA	b'0011 - 50 mA b'0111 - 0.25 A b'1011 - 1.25 A b'1111 - 60 mA
3:0	R/W	IDRIVEP_HS	0x4	High-side gate driver peak source current
3:0	R/W	IDRIVEP_HS	0x4	b'0000 - 10 mA b'0100 - 50 mA b'1000 - 0.25 A b'1100 - 50 mA	b'0001 - 20 mA b'0101 - 60 mA b'1001 - 0.50 A b'1101 - 50 mA	b'0010 - 30 mA b'0110 - 70 mA b'1010 - 0.75 A b'1110 - 50 mA	b'0011 - 40 mA b'0111 - 0.125 A b'1011 - 1.00 A b'1111 - 50 mA

7.6.7.2 LS Gate Driver Control (address = 0x6)

Table 15. LS Gate Driver Control Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R/W	Reserved	0x0
9:8	R/W	TDRIVEP	0x3	Low-side gate driver peak source time b'00 - 250 ns b'01 - 500 ns b'10 - 1000 ns b'11 - 2000 ns
7:4	R/W	IDRIVEN_LS	0x4	Low-side gate driver peak sink current
7:4	R/W	IDRIVEN_LS	0x4	b'0000 - 20 mA b'0100 - 60 mA b'1000 - 0.50 A b'1100 - 60 mA	b'0001 - 30 mA b'0101 - 70 mA b'1001 - 0.75 A b'1101 - 60 mA	b'0010 - 40 mA b'0110 - 80 mA b'1010 - 1.00 A b'1110 - 60 mA	b'0011 - 50 mA b'0111 - 0.25 A b'1011 - 1.25 A b'1111 - 60 mA
3:0	R/W	IDRIVEP_LS	0x4	Low-side gate driver peak source current
3:0	R/W	IDRIVEP_LS	0x4	b'0000 - 10 mA b'0100 - 50 mA b'1000 - 0.25 A b'1100 - 50 mA	b'0001 - 20 mA b'0101 - 60 mA b'1001 - 0.50 A b'1101 - 50 mA	b'0010 - 30 mA b'0110 - 70 mA b'1010 - 0.75 A b'1110 - 50 mA	b'0011 - 40 mA b'0111 - 0.125 A b'1011 - 1.00 A b'1111 - 50 mA

7.6.7.3 Gate Drive Control (address = 0x7)

Table 16. Gate Drive Control Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R/W	Reserved	0x0
9	R/W	COMM_OPTION	0x1	Rectification control (PWM_MODE = b'10 only) b'0 - diode freewheeling b'1 - active freewheeling
8:7	R/W	PWM_MODE	0x0	PWM Mode b'00 - PWM with 6 independent inputs b'01 - PWM with 3 independent inputs b'10 - PWM with one input b'11 - PWM with 6 independent inputs
6:4	R/W	DEAD_TIME	0x1	Dead time
6:4	R/W	DEAD_TIME	0x1	b'000 - 40 ns b'011 - 500 ns b'110 - 4000 ns	b'001 - 60 ns b'100 - 1000 ns b'111 - 6000 ns	b'010 - 100 ns b'101 - 2000 ns
3:2	R/W	TBLANK	0x1	VDS sense blanking b'00 - 0 µs b'01 - 2 µs b'10 - 4 µs b'11 - 8 µs
1:0	R/W	TVDS	0x2	VDS sense deglitch b'00 - 0 µs b'01 - 2 µs b'10 - 4 µs b'11 - 8 µs

7.6.7.4 IC Operation (address = 0x9)

Table 17. IC Operation Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R/W	Flip_OTS	0x0	Enable OTS b'0 - Disable OTS b'1 - Enable OTS
9	R/W	DIS_VPVDD_UVLO2	0x0	Disable PVDD_UVLO2 fault and reporting b'0 - PVDD_UVLO2 enabled b'1 - PVDD_UVLO2 disabled
8	R/W	DIS_GDRV_FAULT	0x0	Disable gate driver fault and reporting b'0 - Gate driver fault enabled b'1 - Gate driver fault disabled
7	R/W	EN_SNS_CLAMP	0x0	Enable sense amplifier clamp b'0 - sense amplifier clamp is not enabled b'1 - sense amplifier clamp is enabled limiting output to about 3.3 V
6:5	R/W	WD_DLY	0x1	Watch dog delay b'00 - 10 ms b'01 - 20 ms b'10 - 50 ms b'11 - 100 ms
4	R/W	DIS_SNS_OCP	0x0	Disable SNS overcurrent protection fault and reporting b'0 - SNS OCP enabled b'1 - SNS OCP disabled
3	R/W	WD_EN	0x0	Watch dog enable b'0 - Watch dog disabled b'1 - Watch dog enabled
2	R/W	SLEEP	0x0	Put device into sleep mode b'0 - Device awake b'1 - Device asleep
1	R/W	CLR_FLTS	0x0	Clear faults b'0 - Normal operation b'1 - Clear fault bits
0	R/W	SET_VCPH_UV	0x0	Set charge pump undervoltage threshold level b'0 - 4.9 V b'1 - 4.6 V

7.6.7.5 Shunt Amplifier Control (address = 0xA)

Table 18. Shunt Amplifier Control Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R/W	DC_CAL_CH3	0x1	DC Calibration of CS amplifier 3 b'0 - Normal operation b'1 - DC calibration mode
9	R/W	DC_CAL_CH2	0x1	DC Calibration of CS amplifier 2 b'0 - Normal operation b'1 - DC calibration mode
8	R/W	DC_CAL_CH1	0x1	DC Calibration of CS amplifier 1 b'0 - Normal operation b'1 - DC calibration mode
7:6	R/W	CS_BLANK	0x0	Current shunt amplifier blanking time b'00 - 0 ns b'01 - 500 ns b'10 - 2.5 µs b'11 - 10 µs
5:4	R/W	GAIN_CS3	0x0	Gain of CS amplifier 3 b'00 - 10 V/V b'01 - 20 V/V b'10 - 40 V/V b'11 - 80 V/V
3:2	R/W	GAIN_CS2	0x0	Gain of CS amplifier 2 b'00 - 10 V/V b'01 - 20 V/V b'10 - 40 V/V b'11 - 80 V/V
1:0	R/W	GAIN_CS1	0x0	Gain of CS amplifier 1 b'00 - 10 V/V b'01 - 20 V/V b'10 - 40 V/V b'11 - 80 V/V

7.6.7.6 Voltage Regulator Control (address = 0xB)

Table 19. Voltage Regulator Control Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10	R/W	Reserved	0x0
9:8	R/W	VREF_SCALING	0x1	VREF Scaling b'00 - RSVD b'01 - k = 2 b'10 - k = 4 b'11 - RSVD
7:5	R/W	Reserved	0x0
4:3	R/W	SLEEP_DLY	0x1	Delay to power down VREG after SLEEP b'00 - 0 µs b'01 - 10 µs b'10 - 50 µs b'11 - 1 ms
2	R/W	DIS_VREG_PWRGD	0x0
0:1	R/W	VREG_UV_LEVEL	0x2	VREG undervoltage set point b'00 - VSET-10% b'01 - VSET-20% b'10 - VSET-30% b'11 - VSET-30%

7.6.7.7 VDS Sense Control (address = 0xC)

Table 20. VDS Sense Control Register Description

BIT	R/W	NAME	DEFAULT	DESCRIPTION
10:8	R/W	Reserved	0x0
7:3	R/W	VDS_LEVEL	0x19	VDS comparator threshold
7:3	R/W	VDS_LEVEL	0x19	b'00000 - 0.060 V b'00100 - 0.097 V b'01000 - 0.155 V b'01100 - 0.250 V b'10000 - 0.403 V b'10100 - 0.648 V b'11000 - 1.043 V b'11100 - 1.679 V	b'00001 - 0.068 V b'00101 - 0.109 V b'01001 - 0.175 V b'01101 - 0.282 V b'10001 - 0.454 V b'10101 - 0.730 V b'11001 - 1.175 V b'11101 - 1.892 V	b'00010 - 0.076 V b'00110 - 0.123 V b'01010 - 0.197V b'01110 - 0.317 V b'10010 - 0.511 V b'10110 - 0.822 V b'11010 - 1.324 V b'11110 - 2.131 V	b'00011 - 0.086 V b'00111 - 0.138 V b'01011 - 0.222 V b'01111 - 0.358 V b'10011 - 0.576 V b'10111 - 0.926 V b'11011 - 1.491 V b'11111 - 2.131 V
2:0	R/W	VDS_MODE	0x0	VDS mode b'000 - Latched shut down when over-current detected b'001 - Report only when over current detected b'010 - VDS protection disabled (no overcurrent sensing or reporting)