ZHCSE35 August   2015 DRV8305

PRODUCTION DATA.  

1. 1 特性
2. 2 應用
3. 3 說明
4. 4 修訂歷史記錄
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 SPI Timing Requirements (Slave Mode Only)
   7. 6.7 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1  Three-Phase Gate Driver
      2. 7.3.2  Operating Modes
      3. 7.3.3  Charge Pump
      4. 7.3.4  Gate Driver Architecture
      5. 7.3.5  IDRIVE/TDRIVE
      6. 7.3.6  Slew Rate/Slope Control
      7. 7.3.7  Current Shunt Amplifiers
      8. 7.3.8  Internal Regulators (DVDD and AVDD)
      9. 7.3.9  Voltage Regulator Output for Driving External Loads (VREG)
      10. 7.3.10 Protection Features
          1. 7.3.10.1 Fault and Protection Handling
          2. 7.3.10.2 Shoothrough Protection
          3. 7.3.10.3 VDS Sensing - External FET Protection and Reporting (OC Event)
          4. 7.3.10.4 Low-Side Source Monitoring (SNS_OCP)
      11. 7.3.11 Undervoltage Reporting and Undervoltage Lockout (UVLO) Protection
          1. 7.3.11.1 Battery Overvoltage Protection (PVDD_OV)
          2. 7.3.11.2 Charge Pump Overvoltage Protection (VCPH_OV/VCP_LSD_OV)
          3. 7.3.11.3 Overtemperature (OT) Warning and Protection
          4. 7.3.11.4 dV/dt Protection
          5. 7.3.11.5 VGS Protection
          6. 7.3.11.6 Gate Driver Faults
          7. 7.3.11.7 Reverse Battery Protection
          8. 7.3.11.8 MCU Watchdog
      12. 7.3.12 Pin Control Functions
          1. 7.3.12.1 EN_GATE
          2. 7.3.12.2 SPI Pins
      13. 7.3.13 Fault / Warning Classes and Recovery
          1. 7.3.13.1 Reg 09h CLR_FLTS
   4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Up and Operating States Hardware Configuration for VREG/VREF
         1. 7.4.1.1 POWER Up
         2. 7.4.1.2 STANDBY State
         3. 7.4.1.3 OPERATING State
         4. 7.4.1.4 SLEEP State
   5. 7.5 Programming
      1. 7.5.1 SPI Communication
         1. 7.5.1.1 SPI
         2. 7.5.1.2 SPI Format
   6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Status Registers
      3. 7.6.3 0x1 Warning and Watchdog Reset
      4. 7.6.4 0x2 OV/VDS Faults
      5. 7.6.5 0x3 IC Faults
      6. 7.6.6 0x4 Gate Driver VGS Faults
      7. 7.6.7 Control Registers
         1. 7.6.7.1 HS Gate Driver Control (address = 0x5)
         2. 7.6.7.2 LS Gate Driver Control (address = 0x6)
         3. 7.6.7.3 Gate Drive Control (address = 0x7)
         4. 7.6.7.4 IC Operation (address = 0x9)
         5. 7.6.7.5 Shunt Amplifier Control (address = 0xA)
         6. 7.6.7.6 Voltage Regulator Control (address = 0xB)
         7. 7.6.7.7 VDS Sense Control (address = 0xC)
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Gate Drive Average Current
         2. 8.2.2.2 MOSFET Slew Rates
         3. 8.2.2.3 Overcurrent Protection
         4. 8.2.2.4 Current Sense Amplifiers
      3. 8.2.3 Application Curves
9. 9 Power Supply Recommendations
   1. 9.1 Bulk Capacitance
10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
11. 11器件和文檔支持
    1. 11.1 社區資源
    2. 11.2 商標
    3. 11.3 靜電放電警告
    4. 11.4 Glossary
12. 12機械、封裝和可訂購信息