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ZHCS138C August 2011 – March 2016 DRV8302

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DCA|56
- MPDS010E

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DCA|56
- PPTD268B

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_PVDD	Supply voltage	Relative to PGND	–0.3	65	V
PVDD_RAMP	Maximum supply voltage ramp rate	Voltage rising up to PVDD_MAX		1	V/µs
V_PGND	Maximum voltage between PGND and GND		–0.3	0.3	V
I_{IN_MAX}	Maximum current, all digital and analog input pins except nFAULT and nOCTW pins		–1	1	mA
I_{IN_OD_MAX}	Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins)			7	mA
V_{OPA_IN}	Voltage range for SPx and SNx pins		–0.6	0.6	V
V_LOGIC	Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL)		–0.3	7	V
V_GVDD	Maximum voltage for GVDD pin			13.2	V
V_AVDD	Maximum voltage for AVDD pin			8	V
V_DVDD	Maximum voltage for DVDD pin			3.6	V
V_REF	Maximum reference voltage for current amplifier			7	V
I_REF	Maximum current for REF Pin			100	µA
T_J	Maximum operating junction temperature		–40	150	°C
T_stg	Storage temperature		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	MAX	UNIT
V_PVDD	DC supply voltage PVDD1 for normal operation	Relative to PGND	8	60	V
V_PVDD	DC supply voltage PVDD2 for buck converter		3.5	60	V
I_{DIN_EN}	Input current of digital pins when EN_GATE is high			100	µA
I_{DIN_DIS}	Input current of digital pins when EN_GATE is low			1	µA
C_{O_OPA}	Maximum output capacitance on outputs of shunt amplifier			20	pF
R_DTC	Dead time control resistor range. Time range is 50 ns (–GND) to 500 ns (150 kΩ) with a linear approximation.		0	150	kΩ
I_FAULT	FAULT pin sink current. Open drain	V = 0.4 V		2	mA
I_OCTW	OCTW pin sink current. Open drain	V = 0.4 V		2	mA
V_REF	External voltage reference voltage for current shunt amplifiers		2	6	V
f_gate	Operating switching frequency of gate driver	Qg(TOT) = 25 nC or total 30-mA gate drive average current		200	kHz
T_A	Ambient temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV8302	UNIT
		DCA (HTSSOP)
		56 PINS
R_θJA	Junction-to-ambient thermal resistance	30.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	33.5	°C/W
R_θJB	Junction-to-board thermal resistance	17.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.9	°C/W
ψ_JB	Junction-to-board characterization parameter	7.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

PVDD = 8 V to 60 V, T_C = 25°C, unless specified under test condition

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL
V_IH	High input threshold		2			V
V_IL	Low input threshold				0.8	V
R_{EN_GATE}	Internal pulldown resistor for EN_GATE			100		kΩ
R_{INH_X}	Internal pulldown resistor for high side PWMs (INH_A, INH_B, and INH_C)	EN_GATE high		100		kΩ
R_{INH_X}	Internal pulldown resistor for low side PWMs (INL_A, INL_B, and INL_C)	EN_GATE high		100		kΩ
R_{M_PWM}	Internal pulldown resistor for M_PWM	EN_GATE high		100		kΩ
R_{M_OC}	Internal pulldown resistor for M_OC	EN_GATE high		100		kΩ
R_{DC_CAL}	Internal pulldown resistor for DC_CAL	EN_GATE high		100		kΩ
OUTPUT PINS: nFAULT AND nOCTW
V_OL	Low output threshold	I_O = 2 mA			0.4	V
V_OH	High output threshold	External 47-kΩ pullup resistor connected to 3-5.5 V	2.4			V
I_OH	Leakage current on open-drain pins When logic high (nFAULT and nOCTW)				1	µA
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
V_{GX_NORM}	Gate driver Vgs voltage	PVDD = 8 V to 60 V	9.5		11.5	V
I_oso1	Maximum source current setting 1, peak	Vgs of FET equals to 2 V		1.7		A
I_osi1	Maximum sink current setting 1, peak	Vgs of FET equals to 8 V		2.3		A
R_{gate_off}	Gate output impedance during standby mode when EN_GATE low (pins GH_x, GL_x)		1.6		2.4	kΩ
SUPPLY CURRENTS
I_{PVDD1_STB}	PVDD1 supply current, standby	EN_GATE is low. PVDD1 = 8 V.		20	50	µA
I_{PVDD1_OP}	PVDD1 supply current, operating	EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100-nC gate charge		15		mA
I_{PVDD1_HIZ}	PVDD1 Supply current, HiZ	EN_GATE is high, gate not switching	2	5	11	mA
INTERNAL REGULATOR VOLTAGE
A_VDD	AVDD voltage		6	6.5	7	V
D_VDD	DVDD voltage		3	3.3	3.6	V
VOLTAGE PROTECTION
V_{PVDD_UV}	Undervoltage protection limit, PVDD				6	V
V_{GVDD_UV}	Undervoltage protection limit, GVDD				8	V
V_{GVDD_OV}	Overvoltage protection limit, GVDD			16		V
CURRENT PROTECTION, (VDS SENSING)
V_{DS_OC}	Drain-source voltage protection limit		0.125		2.4	V
T_oc	OC sensing response time			1.5		µs
T_{OC_PULSE}	OCTW pin reporting pulse stretch length for OC event			64		µs

6.6 Gate Timing and Protection Characteristics

			MIN	NOM	MAX	UNIT
TIMING, OUTPUT PINS
t_pd,If-O	Positive input falling to GH_x falling	CL=1 nF, 50% to 50%		45		ns
t_pd,Ir-O	Positive input rising to GL_x falling	CL=1 nF, 50% to 50%		45		ns
T_{d_min}	Minimum dead time after hand shaking⁽¹⁾				50	ns
T_dtp	Dead Time	With R_DTC set to different values	50		500	ns
t_GDr	Rise time, gate drive output	CL=1 nF, 10% to 90%		25		ns
t_GDF	Fall time, gate drive output	CL=1 nF, 90% to 10%		25		ns
T_{ON_MIN}	Minimum on pulse	Not including handshake communication. Hiz to on state, output of gate driver			50	ns
T_{pd_match}	Propagation delay matching between high side and low side				5	ns
T_{dt_match}	Deadtime matching				5	ns
TIMING, PROTECTION AND CONTROL
t_{pd,R_GATE-OP}	Start-up time, from EN_GATE active high to device ready for normal operation	PVDD is up before start-up, all charge pump caps and regulator caps as in recommended condition		5	10	ms
t_{pd,R_GATE-Quick}	If EN_GATE goes from high to low and back to high state within quick reset time, it will only reset all faults and gate driver without powering down charge pump, current amp, and related internal voltage regulators.	Maximum low pulse time			10	us
t_pd,E-L	Delay, error event to all gates low			200		ns
t_pd,E-FAULT	Delay, error event to FAULT low			200		ns
OTW_CLR	Junction temperature for resetting overtemperature warning			115		°C
OTW_SET/OTSD_CLR	Junction temperature for overtemperature warning and resetting overtemperature shut down			130		°C
OTSD_SET	Junction temperature for overtemperature shut down			150		°C

(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.

6.7 Current Shunt Amplifier Characteristics

T_C = 25°C unless otherwise specified

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
G1	Gain option 1	(GAIN = 0 V)	9.5	10	10.5	V/V
G2	Gain option 2	(GAIN = 2 V)	38	40	42	V/V
Tsettling	Settling time to 1%	Tc = 0°C to 60°C, G = 10, Vstep = 2 V		300		ns
Tsettling	Settling time to 1%	Tc = 0°C to 60°C, G = 40, Vstep = 2 V		1.2		µs
Vswing	Output swing linear range		0.3		5.7	V
Slew Rate		G = 10		10		V/µs
DC_offset	Offset error RTI	G = 10 with input shorted			4	mV
Drift_offset	Offset drift RTI			10		µV/C
Ibias	Input bias current				100	µA
Vin_com	Common input mode range		–0.15		0.15	V
Vin_dif	Differential input range		–0.3		0.3	V
Vo_bias	Output bias	With zero input current, Vref up to 6 V	–0.5%	0.5×Vref	0.5%	V
CMRR_OV	Overall CMRR with gain resistor mismatch	CMRR at DC, gain = 10	70	85		dB

6.8 Buck Converter Characteristics

T_C = 25°C unless otherwise specified

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_UVLO	Internal undervoltage lockout threshold	No voltage hysteresis, rising and falling		2.5		V
I_SD(PVDD2)	Shutdown supply current	EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V		1.3	4	µA
I_{NON_SW(PVDD2)}	Operating: nonswitching supply current	VSENSE = 0.83 V, VIN = 12 V		116	136	µA
V_{EN_BUCK}	Enable threshold voltage	No voltage hysteresis, rising and falling	1.11	1.25	1.36	V
R_{DS_ON}	On-resistance	VIN = 12 V, BOOT-PH = 6 V		200	410	mΩ
I_LIM	Current limit threshold	VIN = 12 V, T_J = 25°C	1.8	2.7		A
OTSD_BK	Thermal shutdown			150		°C
F_sw	Switching frequency	RT = 200 kΩ	450	581	720	kHz
PWRGD	VSENSE threshold	VSENSE falling		92%
		VSENSE rising		94%
		VSENSE rising		109%
		VSENSE falling		107%
	Hysteresis	VSENSE falling		2%
	Output high leakage	VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C		10		nA
	On resistance	I(PWRGD) = 3 mA, VSENSE < 0.79 V		50		Ω

6.9 Typical Characteristics

Figure 1. I_PVDD1 vs Temperature
(PVDD1 = 8 V, EN_GATE = LOW)

Figure 3. GVDD vs Temperature (PVDD1 = 60 V, EN_GATE = HIGH)

Figure 2. GVDD vs Temperature
(PVDD1 = 8 V, EN_GATE = HIGH)