Since the DRV8251A integrates power
MOSFETs capable of driving high current, careful attention should be paid to the
layout design and external component placement. Some design and layout guidelines
are provided below.
- Low ESR ceramic capacitors should be utilized for the VM to GND bypass
capacitor. X5R and X7R types are recommended.
- The VM power supply capacitors should be placed as close to the device as
possible to minimize the loop inductance.
- The VM power supply bulk capacitor can be of ceramic or electrolytic type, but
should also be placed as close as possible to the device to minimize the loop
inductance.
- VM, OUT1, OUT2, and GND
carry the high current from the power supply to the outputs and back to ground.
Thick metal routing should be utilized for these traces as is feasible.
- The device thermal pad should be attached to the PCB top layer ground plane and
internal ground plane (when available) through thermal vias to maximize the PCB
heat sinking.
- A recommended land pattern for the thermal vias is provided in the package
drawing section.
- The copper plane area attached to the thermal pad should be maximized to ensure
optimal heat sinking.