SLVSDM3 February 2017 DRV3220-Q1
PRODUCTION DATA.
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | GLS3 | PWR | Gate low-side 3, connected to gate of external power MOSFET. |
| 2 | SLS3 | PWR | Source low-side 3, connected to external power MOSFET for gate discharge and VDS monitoring. |
| 3 | GHS3 | PWR | Gate high-side 3, connected to gate of external power MOSFET. |
| 4 | SHS3 | PWR | Source high-side 3, connected to external power MOSFET for gate discharge and VDS monitoring. |
| 5 | VSH | HVI_A | Sense high-side, sensing VS connection of the external power MOSFETs for VDS monitoring. |
| 6 | SHS2 | PWR | Source high-side 2, connected to external power MOSFET gate discharge and VDS monitoring. |
| 7 | GHS2 | PWR | Gate high-side 2, connected to gate of external power MOSFET. |
| 8 | SLS2 | PWR | Source low-side 2, connected to external power MOSFET for gate discharge and VDS monitoring. |
| 9 | GLS2 | PWR | Gate low-side 2, connected to gate of external power MOSFET. |
| 10 | TEST | HVI_A | Test mode input, during normal application connected to ground. |
| 11 | GLS1 | PWR | Gate low-side 1, connected to gate of external power MOSFET. |
| 12 | SLS1 | PWR | Source low-side 1, connected to external power MOSFET for gate discharge and VDS monitoring. |
| 13 | GHS1 | PWR | Gate high-side 1, connected to gate of external power MOS transistor. |
| 14 | SHS1 | PWR | Source high-side 1, connected to external power MOS transistor for gate discharge and VDS. |
| 15 | VS | Supply | Power-supply voltage (externally protected against reverse battery connection). |
| 16 | GNDA | GND | Analog ground. |
| 17 | ERR | LVO_D | Error (low active), Error pin to indicate detected error. |
| 18 | DRVOFF | HVI_D | Driver OFF (high active), secondary bridge driver disable. |
| 19 | RVSET | HVI_A | VDDIO / ADREF OV/UV configuration resister. |
| 20 | BOOST | Supply | Boost output voltage, used as supply for the gate drivers. |
| 21 | SW | PWR | Boost converter switching node connected to external coil and external diode. |
| 22 | NCS | HVI_D | SPI chip select. |
| 23 | GNDLS_B | GND | Boost GND to set current limit. Boost switching current goes through this pin through external resistor to ground. |
| 24 | EN | HVI_D | Enable (high active) of the device. |
| 25 | VDDIO | Supply | I/O supply voltage, defines the interface voltage of digital I/O, for example, SPI. |
| 26 | SCLK | HVI_D | SPI clock. |
| 27 | SDO | LVO_D | SPI data output. |
| 28 | SDI | HVI_D | SPI data input. |
| 29 | VCC3 | LVO_A | VCC3 regulator, for internal use only. TI recommends an external decoupling capacitor of 0.1 µF. External load < 100 µA. |
| 30 | GNDA | GND | Analog ground. |
| 31 | NU | — | Not used. Leave this pin open. |
| 32 | VCC5 | LVO_A | VCC5 regulator, for internal use only. Recommended external decoupling capacitor 1 µF. External load < 100 µA. |
| 33 | ADREF | LVI_A | ADC reference of MCU. Connect to VDDIO |
| 34 | NU | — | Not used. Leave this pin open. |
| 35 | NU | — | Not used. Leave this pin open. |
| 36 | NU | — | Not used. Leave this pin open. |
| 37 | NU | — | Not used. Connect this pin to ground. |
| 38 | NU | — | Not used. Connect this pin to ground. |
| 39 | NU | — | Not used. Connect this pin to ground. |
| 40 | NU | — | Not used. Connect this pin to ground. |
| 41 | NU | — | Not used. Connect this pin to ground. |
| 42 | NU | — | Not used. Connect this pin to ground. |
| 43 | IHS3 | HVI_D | High-side input 3, digital input to drive the HS3. |
| 44 | IHS2 | HVI_D | Input HS 2, digital input to drive the HS2. |
| 45 | IHS1 | HVI_D | Input HS 1, digital input to drive the HS1. |
| 46 | ILS3 | HVI_D | Low-side input 3, digital input to drive the LS3. |
| 47 | ILS2 | HVI_D | Input LS 2, digital input to drive the LS2. |
| 48 | ILS1 | HVI_D | Input LS 1, digital input to drive the LS1. |