ZHCSFI6E September 2015 – February 2017 DRV3205-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PHP|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PHP|48
訂購(gòu)信息
10 Layout
10.1 Layout Guidelines
Use the following guidelines when designing a PCB for the DRV3205-Q1:
- In addition to the GND pins, the DRV3205-Q1 makes an electrical connection to GND through the PowerPAD. Always check that the PowerPAD has been properly soldered (see PowerPAD™ Thermally Enhanced Package [SLMA002]).
- The VS bypass capacitors should be placed close to the power supply terminals. See the VS box in Figure 19
- Place the VCC5 and VCC5 bypass capacitors close to the corresponding pins with a low impedance path to the ground plane pin (pin 16). See the VCC3 VCC5 bypass box in Figure 19.
- AGND should all be tied to the ground plane through a low impedance trace or copper fill.
- Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
- Try to clear the space around and below the DRV3205-Q1 to allow for better heat spreading from the PowerPAD.
- Route the sense lines, IPx and INx, each with a unique trace, directly to either side of the sense resistor. See the SENSE box in Figure 19.
- Keep the BOOST components close to the device and current loops small. See the BOOST boxes in Figure 19.
- Place the current sense resistors close to the respective low-side FET. See the SENSE box in Figure 19.
- Place the GNDLS_B resistor close to the device pin. See the GNDLS_B box in Figure 19.
10.2 Layout Example
Figure 19. Layout Schematic