ZHCSEY6E March 2013 – January 2023 DRV2667
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Support for Haptic Piezo Actuators
- 7.3.2 Flexible Front End Interface
- 7.3.3 Ramp Down Behavior
- 7.3.4 Low Latency Startup
- 7.3.5 Low Power Standby Mode
- 7.3.6 Device Reset
- 7.3.7 Amplifier Gain
- 7.3.8 Adjustable Boost Voltage
- 7.3.9 Adjustable Current Limit
- 7.3.10 Internal Charge Pump
- 7.3.11 Device Protection
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.5.4.5 Single-Byte Read
Figure 7-13 shows that a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read-write bit. For the data-read transfer, both a write followed by a read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be read. As a result, the read-write bit is set to 0.
After receiving the DRV2667 address and the read-write bit, the DRV2667 device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the DRV2667 address and the read-write bit again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2667 device transmits the data byte from the memory address that is read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. See the note in the Section 7.5.4.1 section for the device address.
Figure 7-13 Single-Byte Read Transfer