ZHCSQL1 May 2022 DP83TC813R-Q1 , DP83TC813S-Q1
PRODUCTION DATA
The DP83TC813S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register access). Some strap pins support 3 levels and some strap pins support 2 levels, which are described in greater detail below. PHY address straps, RX_DV/RX_CTRL and RX_ER, are 3-level straps while all other straps are two levels. Configuration of the device may be done through strapping or through serial management interface.
Because strap pins are functional pins after reset is deasserted, they must not be connected directly to VDDIO or VDDMAC or GND. Either pullup resistors, pulldown resistors, or both are required for proper operation.
When using VDDMAC and VDDIO separately, it is important to connect strap resistors to the correct voltage rail. Each pin's voltage domain is listed in the Table 8-18 table below.
Rpulldn value is included in the Electrical Characteristics table of the data sheet.
| MODE3 | IDEAL RH (k?) (VDDIO = 3.3V)1 | IDEAL RH (k?) (VDDIO = 2.5V)2 | IDEAL RH (k?) (VDDIO = 1.8V)1 |
|---|---|---|---|
| 1 | OPEN | OPEN | OPEN |
| 2 | 13 | 12 | 4 |
| 3 | 4.5 | 2 | 0.8 |
The following table describes the PHY configuration bootstraps:
| PIN NAME |
PIN NO. | DOMAIN | DEFAULT MODE |
STRAP FUNCTION | DESCRIPTION | ||
|---|---|---|---|---|---|---|---|
| RX_DV/RX_CTRL | 13 | VDDMAC | 1 | MODE | PHY_AD[0] | PHY_AD[2] | PHY_AD: PHY Address ID |
| 1 | 0 | 0 | |||||
| 2 | 0 | 1 | |||||
| 3 | 1 | 1 | |||||
| RX_ER | 21 | VDDMAC | 1 | MODE | PHY_AD[1] | PHY_AD[3] | PHY_AD: PHY Address ID |
| 1 | 0 | 0 | |||||
| 2 | 0 | 1 | |||||
| 3 | 1 | 1 | |||||
| RX_CLK | 28 | VDDMAC | 1 | MODE | AUTO | AUTO: Autonomous Disable. | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D0 | 27 | VDDMAC | 1 | MODE | MAC[0] | MAC: MAC Interface Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D1 | 26 | VDDMAC | 1 | MODE | MAC[1] | MAC: MAC Interface Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D2 | 25 | VDDMAC | 1 | MODE | MAC[2] | MAC: MAC Interface Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| RX_D3 | 24 | VDDMAC | 1 | MODE | MS | MS: 100BASE-T1 Master and 100BASE-T1 Slave Selection | |
| 1 | 0 | ||||||
| 2 | 1 | ||||||
| MS | DESCRIPTION |
|---|---|
| 0 | 100BASE-T1 Slave Configuration |
| 1 | 100BASE-T1 Master Configuration |
| AUTO | DESCRIPTION |
|---|---|
| 0 | Autonomous Mode, PHY able to establish link after power-up |
| 1 | Managed Mode, PHY must be allowed to establish link after power-up based on register write |
| MAC[2] | MAC[1] | MAC[0] | DESCRIPTION |
|---|---|---|---|
| 0 | 0 | 0 | SGMII (4-wire)(1) |
| 0 | 0 | 1 | MII |
| 0 | 1 | 0 | RMII Slave |
| 0 | 1 | 1 | RMII Master |
| 1 | 0 | 0 | RGMII (Align Mode) |
| 1 | 0 | 1 | RGMII (TX Internal Delay Mode) |
| 1 | 1 | 0 | RGMII (TX and RX Internal Delay Mode) |
| 1 | 1 | 1 | RGMII (RX Internal Delay Mode) |
| PHY_AD[3:0] | RX_CTRL STRAP MODE | RX_ER STRAP MODE | DESCRIPTIONSection 8.5.1 |
|---|---|---|---|
| 0000 | 1 | 1 | PHY Address: 0b00000 (0x0) |
| 0001 | - | - | NA |
| 0010 | - | - | NA |
| 0011 | - | - | NA |
| 0100 | 2 | 1 | PHY Address: 0b00100 (0x4) |
| 0101 | 3 | 1 | PHY Address: 0b00101 (0x5) |
| 0110 | - | - | NA |
| 0111 | - | - | NA |
| 1000 | 1 | 2 | PHY Address: 0b01000 (0x8) |
| 1001 | - | - | NA |
| 1010 | 1 | 3 | PHY Address: 0b01010 (0xA) |
| 1011 | - | - | NA |
| 1100 | 2 | 2 | PHY Address: 0b01010 (0xC) |
| 1101 | 3 | 2 | PHY Address: 0b01011 (0xD) |
| 1110 | 2 | 3 | PHY Address: 0b01110 (0xE) |
| 1111 | 3 | 3 | PHY Address: 0b01111 (0xF) |