SNOSAX1F May 2008 – September 2015 DP83849I
PRODUCTION DATA.
- 1 Device Overview
- 2 Revision History
- 3 Terminal Configuration and Functions
- 4 Specifications
-
5 Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3 Feature Description
- 5.4 Device Functional Modes
- 5.5
Programming
- 5.5.1 Architecture
- 5.5.2 100BASE-TX Receiver
- 5.5.3
Analog Front End
- 5.5.3.1 Digital Signal Processor
- 5.5.3.2 Digital Adaptive Equalization and Gain Control
- 5.5.3.3 Signal Detect
- 5.5.3.4 MLT-3 to NRZI Decoder
- 5.5.3.5 NRZI to NRZ
- 5.5.3.6 Serial to Parallel
- 5.5.3.7 Descrambler
- 5.5.3.8 Code-Group Alignment
- 5.5.3.9 4B/5B Decoder
- 5.5.3.10 100BASE-TX Link Integrity Monitor
- 5.5.3.11 BAD SSD Detection
- 5.5.4
10BASE-T Transceiver Module
- 5.5.4.1 Operational Modes
- 5.5.4.2 Smart Squelch
- 5.5.4.3 Collision Detection and SQE
- 5.5.4.4 Carrier Sense
- 5.5.4.5 Normal Link Pulse Detection/Generation
- 5.5.4.6 Jabber Function
- 5.5.4.7 Automatic Link Polarity Detection and Correction
- 5.5.4.8 Transmit and Receive Filtering
- 5.5.4.9 Transmitter
- 5.5.4.10 Receiver
- 5.6
Register Block
- 5.6.1
Register Definition
- 5.6.1.1 Basic Mode Control Register (BMCR)
- 5.6.1.2 Basic Mode Status Register (BMSR)
- 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
- 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
- 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
- 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
- 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
- 5.6.1.10 PHY Status Register (PHYSTS)
- 5.6.1.11 MII Interrupt Control Register (MICR)
- 5.6.1.12 MII Interrupt Status and Miscellaneous Control Register (MICR)
- 5.6.1.13 Page Select Register (PAGESEL)
- 5.6.2
Extended Registers - Page 0
- 5.6.2.1 False Carrier Sense Counter Register (FCSCR)
- 5.6.2.2 Receiver Error Counter Register (RECR)
- 5.6.2.3 100 Mb/s PCS Configuration and Status Register (PCSR)
- 5.6.2.4 RMII and Bypass Register (RBR)
- 5.6.2.5 LED Direct Control Register (LEDCR)
- 5.6.2.6 PHY Control Register (PHYCR)
- 5.6.2.7 10BASE-T Status/Control Register (10BTSCR)
- 5.6.2.8 CD Test and BIST Extensions Register (CDCTRL1)
- 5.6.2.9 Phy Control Register 2 (PHYCR2)
- 5.6.2.10 Energy Detect Control (EDCR)
- 5.6.3
Link Diagnostics Registers - Page 2
- 5.6.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h
- 5.6.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h
- 5.6.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h
- 5.6.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h
- 5.6.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h
- 5.6.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h
- 5.6.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah
- 5.6.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh
- 5.6.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh
- 5.6.3.10 Link Quality Data Register (LQDR), Page 2
- 5.6.1
Register Definition
- 6 Applications, Implementation, and Layout
- 7 Power Supply Recommendations
- 8 Layout
- 9 Device and Documentation Support
- 10Mechanical Packaging and Orderable Information
1 Device Overview
1.1 Features
- Low-power 3.3-V, 0.18-µm CMOS Technology
- Low power Consumption <600 mW Typical
- 3.3-V MAC Interface
- Auto-MDIX for 10/100 Mb/s
- Energy Detection Mode
- Flexible MII Port Assignment
- Dynamic Integrity Utility
- Dynamic Link Quality Monitoring
- TDR based Cable Diagnostic and Cable Length Detection
- Optimized Latency for Real-Time Ethernet Operation
- Reference Clock Out
- RMII Rev. 1.2 Interface (Configurable)
- SNI Interface (Configurable)
- MII Serial Management Interface (MDC and MDIO)
- IEEE 802.3u MII
- IEEE 802.3u Auto-Negotiation and Parallel Detection
- IEEE 802.3u ENDEC, 10BASE-T Transceivers and Filters
- IEEE 802.3u PCS, 100BASE-TX Transceivers and Filters
- IEEE 1149.1 JTAG
- Integrated ANSI X3.263 Compliant TP-PMD Physical Sub-layer with Adaptive Equalization and Baseline Wander Compensation
- Programmable LED Support for Link, 10/100 Mb/s Mode, Activity, Duplex and Collision Detect
- Single Register Access for Complete PHY Status
- 10/100 Mb/s Packet BIST (Built-In Self Test)
- 80-pin TQFP Package (12-mm × 12-mm)
1.2 Applications
- Medical Instrumentation
- Factory Automation
- Motor and Motion Control
- Wireless Remote Base Station
- General Embedded Applications
1.3 Description
The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements. Where single channel Ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require DUAL Port functionality for redundancy or system management.
The DP83849I is a highly reliable, feature rich device perfectly suited for industrial applications enabling Ethernet on the factory floor. The DP83849I features two fully independent 10/100 ports for multi-port applications. The unique port switching capability also allows the two ports to be configured to provide fully integrated range extension, media conversion, hardware based failover and port monitoring.
The DP83849I provides optimum flexibility in MPU selection by supporting both MII and RMII interfaces. In addition this device includes a powerful new diagnostics tool to ensure initial network operation and maintenance.
In addition to the TDR scheme, commonly used for detecting faults during installation, the innovative cable diagnostics provides for real time continuous monitoring of the link quality. This allows the system designer to implement a fault prediction mechanism to detect and warn of changing or deteriorating link conditions.
The DP83849I continues to build on its Ethernet expertise and leadership position by providing a powerful combination of features and flexibility, easing Ethernet implementation for the system designer.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE |
|---|---|---|
| DP83849I | TQFP (80) | 12.00 mm × 12.00 mm |
1.4 System Diagram
