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SNLS250E May 2008 – April 2015 DP83848H , DP83848J , DP83848K , DP83848M , DP83848T

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTA|40
- MPQF134A

散熱焊盤機械數據 (封裝 | 引腳)

RTA|40
- QFND447B

訂購信息

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_CC	Supply voltage	–0.5	4.2	V
V_IN	DC input voltage	–0.5	V_CC + 0.5	V
V_OUT	DC output voltage	–0.5	V_CC + 0.5	V
	Max case temperature		147.7	°C
T_J	Max die temperature		150	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All parameters are specified by test, statistical analysis or design.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽³⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) R_ZAP = 1.5 kΩ, C_ZAP = 120 pF

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Supply voltage		3.3	±0.3	V
T_A	Ambient temperature	Commerical - DP83848J/M	0	70	°C
		Industrial - DP83848K/T	–40	85
		Extreme - DP83848H	–40	125
P_D	Power dissipation			264	mW

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		DP83848x	UNIT
		RTA [WQFN]
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	31.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	8.8
R_θJB	Junction-to-board thermal resistance	40.5
ψ_JT	Junction-to-top characterization parameter	0.4
ψ_JB	Junction-to-board characterization parameter	10.5
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	5.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5.5 DC Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	PIN TYPES	MIN	TYP	MAX	UNIT
V_IH	Input high voltage	Nominal V_CC	I I/O	2			V
V_IL	Input low voltage		I I/O			0.8	V
I_IH	Input high current	V_IN = V_CC	I I/O			10	µA
I_IL	Input low current	V_IN = GND	I I/O			10	µA
V_OL	Output low voltage	I_OL = 4 mA	O, I/O			0.4	V
V_OH	Output high voltage	I_OH = –4 mA	O, I/O	Vcc – 0.5			V
V_ledOL	Output low voltage	I_OL = 2.5 mA	LED			0.4	V
V_ledOH	Output high voltage	I_OH = –2.5 mA	LED	Vcc – 0.5			V
I_OZ	Tri-state leakage	V_OUT = V_CC	I/O, O			±10	µA
V_{TPTD_100}	100M Transmit voltage		PMD Output	0.95	1	1.05	V
V_TPTDsym	100M Transmit voltage symmetry		PMD Output Pair			±2%
V_{TPTD_10}	10M Transmit voltage		PMD Output Pair	2.2	2.5	2.8	V
C_IN1	CMOS Input capacitance		I		5		pF
C_OUT1	CMOS Output capacitance		O		5		pF
SD_THon	100BASE-TX Signal detect turnon threshold		PMD Input Pair			1000	mV diff pk-pk
SD_THoff	100BASE-TX Signal detect turnoff threshold		PMD Input Pair	200			mV diff pk-pk
V_TH1	10BASE-T Receive Threshold		PMD Input Pair			585	mV
I_dd100	100BASE-TX (Full Duplex)	I_OUT = 0 mA⁽¹⁾	PMD Input Pair		81		mA
I_dd10	10BASE-T (Full Duplex)	I_OUT = 0 mA⁽¹⁾	Supply		92		mA

(1) Refer to application note SNLA089, “Power Measurement of Ethernet Physical Layer Products”

5.6 AC Timing Requirements

			MIN	NOM	MAX	UNIT
POWER UP TIMING (REFER TO Figure 5-1)⁽¹⁾
T2.1.1	Post Power Up Stabilization time prior to MDC preamble for register accesses	MDIO is pulled high for 32-bit serial management initialization. X1 Clock must be stable for a minimum of 167 ms at power up.	167			ms
T2.1.2	Hardware Configuration Latch-in Time from power up	Hardware Configuration Pins are described in Section 4. X1 Clock must be stable for a minimum of 167 ms at power up.	167			ms
T2.1.3	Hardware Configuration pins transition to output drivers			50		ns
RESET TIMING (REFER TO Figure 5-2)⁽²⁾
T2.2.1	Post RESET Stabilization time prior to MDC preamble for register accesses	MDIO is pulled high for 32-bit serial management initialization.		3		µs
T2.2.2	Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard)	Hardware Configuration Pins are described in Section 4.		3		µs
T2.2.3	Hardware Configuration pins transition to output drivers			50		ns
T2.2.4	RESET pulse width	X1 Clock must be stable for at minimum of 1 µs during RESET pulse low time.	1			µs
MII SERIAL MANAGEMENT TIMING (REFER TO Figure 5-3)
T2.3.1	MDC to MDIO (Output) Delay Time		0		30	ns
T2.3.2	MDIO (Input) to MDC Setup Time		10			ns
T2.3.3	MDIO (Input) to MDC Hold Time		10			ns
T2.3.4	MDC Frequency			2.5	25	MHz
100 Mb/s MII TRANSMIT TIMING (REFER TO Figure 5-4)
T2.4.1	TX_CLK High/Low Time	100 Mb/s Normal mode	16	20	24	ns
T2.4.2	TXD[3:0], TX_EN Data Setup to TX_CLK	100 Mb/s Normal mode	10			ns
T2.4.3	TXD[3:0], TX_EN Data Hold from TX_CLK	100 Mb/s Normal mode	0			ns
100 Mb/s MII RECEIVE TIMING (REFER TO Figure 5-5)⁽³⁾
T2.5.1	RX_CLK High/Low Time	100 Mb/s Normal mode	16	20	24	ns
T2.5.2	RX_CLK to RXD[3:0], RX_DV, RX_ER Delay	100 Mb/s Normal mode	10		30	ns
100BASE-TX TRANSMIT PACKET LATENCY TIMING (REFER TO Figure 5-6)⁽⁴⁾
T2.6.1	TX_CLK to PMD Output Pair Latency	100 Mb/s Normal mode		6		bits
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING (REFER TO Figure 5-7)⁽⁵⁾
T2.7.1	TX_CLK to PMD Output Pair Deassertion	100 Mb/s Normal mode		6		bits
100BASE-TX TRANSMIT TIMING (t_R/F) AND JITTER) (REFER TO Figure 5-8)⁽⁶⁾⁽⁷⁾
T2.8.1	100 Mb/s PMD Output Pair t_R and t_F		3	4	5	ns
T2.8.1	100 Mb/s t_R and t_F Mismatch				500	ps
T2.8.2	100 Mb/s PMD Output Pair Transmit Jitter				1.4	ns
100BASE-TX RECEIVE PACKET LATENCY TIMING (REFER TO Figure 5-9)⁽⁸⁾⁽⁹⁾⁽¹⁰⁾
T2.9.1	Carrier Sense ON Delay	100 Mb/s Normal mode		20		bits
T2.9.2	Receive Data Latency	100 Mb/s Normal mode		24		bits
100BASE-TX RECEIVE PACKET DEASSERTION TIMING (REFER TO Figure 5-10)⁽⁹⁾⁽¹¹⁾
T2.10.1	Carrier Sense OFF Delay	100 Mb/s Normal mode		24		bits
10 Mb/s MII TRANSMIT TIMING (REFER TO Figure 5-11)⁽¹²⁾
T2.11.1	TX_CLK High/Low Time	10 Mb/s MII mode	190	200	210	ns
T2.11.2	TXD[3:0], TX_EN Data Setup to TX_CLK fall	10 Mb/s MII mode	25			ns
T2.11.3	TXD[3:0], TX_EN Data Hold from TX_CLK rise	10 Mb/s MII mode	0			ns
10 Mb/s MII RECEIVE TIMING (REFER TOFigure 5-12)⁽¹³⁾
T2.12.1	RX_CLK High/Low Time		160	200	240	ns
T2.12.2	RX_CLK to RXD[3:0], RX_DV Delay	10 Mb/s MII mode	100			ns
T2.12.3	RX_CLK rising edge delay from RXD[3:0], RX_DV Valid	10 Mb/s MII mode	100			ns
10BASE-T TRANSMIT TIMING (START OF PACKET) (REFER TO Figure 5-13)⁽¹⁴⁾
T2.13.1	Transmit Output Delay from the Falling Edge of TX_CLK	10 Mb/s MII mode		3.5		bits
10BASE-T TRANSMIT TIMING (END OF PACKET) (REFER TO Figure 5-14)
T2.14.1	End of Packet High Time (with 0 ending bit)		250	300		ns
T2.14.2	End of Packet High Time (with 1 ending bit)		250	300		ns
10BASE-T RECEIVE TIMING (START OF PACKET) (REFER TO Figure 5-15)⁽¹⁴⁾⁽¹⁵⁾
T2.15.1	Carrier Sense Turnon Delay (PMD Input Pair to CRS)			630	1000	ns
T2.15.2	RX_DV Latency			10		bits
T2.15.3	Receive Data Latency	Measurement shown from SFD		8		bits
10BASE-T RECEIVE TIMING (END OF PACKET) (REFER TO Figure 5-16)
T2.16.1	Carrier Sense Turn Off Delay				1	µs
10Mb/s HEARTBEAT TIMING (REFER TO Figure 5-17)
T2.17.1	CD Heartbeat Delay	All 10 Mb/s modes		1200		ns
T2.17.2	CD Heartbeat Duration	All 10 Mb/s modes		1000		ns
10 Mb/s JABBER TIMING (REFER TO Figure 5-18)
T2.18.1	Jabber Activation Time			85		ms
T2.18.2	Jabber Deactivation Time			500		ms
10BASE-T NORMAL LINK PULSE TIMING (REFER TO Figure 5-19)⁽¹⁶⁾
T2.19.1	Pulse Width			100		ns
T2.19.2	Pulse Period			16		ms
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING (REFER TO Figure 5-20)⁽¹⁶⁾
T2.20.1	Clock, Data Pulse Width			100		ns
T2.20.2	Clock Pulse to Clock Pulse Period			125		µs
T2.20.3	Clock Pulse to Data Pulse Period	Data = 1		62		µs
T2.20.4	Burst Width			2		ms
T2.20.5	FLP Burst to FLP Burst Period			16		ms
100BASE-TX SIGNAL DETECT TIMING (REFER TO Figure 5-22)⁽¹⁷⁾
T2.21.1	SD Internal Turnon Time				1	ms
T2.21.2	SD Internal Turnoff Time				350	µs
100 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 5-22)⁽¹⁸⁾⁽¹⁹⁾
T2.22.1	TX_EN to RX_DV Loopback	100 Mb/s internal loopback mode			240	ns
10 Mb/s INTERNAL LOOPBACK TIMING (REFER TO Figure 5-23)⁽¹⁹⁾
T2.23.1	TX_EN to RX_DV Loopback	10 Mb/s internal loopback mode			2	µs
RMII TRANSMIT TIMING (REFER TO Figure 5-24)
T2.24.1	X1 Clock Period	50-MHz Reference Clock		20		ns
T2.24.2	TXD[1:0], TX_EN, Data Setup to X1 rising		4			ns
T2.24.3	TXD[1:0], TX_EN, Data Hold from X1 rising		2			ns
T2.24.4	X1 Clock to PMD Output Pair Latency	From X1 Rising edge to first bit of symbol		17		bits
RMII RECEIVE TIMING (REFER TO Figure 5-25)⁽²⁰⁾⁽²¹⁾⁽²²⁾⁽²³⁾⁽²⁴⁾⁽²⁵⁾
T2.25.1	X1 Clock Period	50-MHz Reference Clock		20		ns
T2.25.2	RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising		2		14	ns
T2.25.3	CRS ON delay	From JK symbol on PMD Receive Pair to initial assertion of CRS_DV		18.5		bits
T2.25.4	CRS OFF delay	From TR symbol on PMD Receive Pair to initial deassertion of CRS_DV		27		bits
T2.25.5	RXD[1:0] and RX_ER latency	From symbol on Receive Pair. Elasticity buffer set to default value (01)		38		bits
ISOLATION TIMING (REFER TO Figure 5-26)
T2.26.1	From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode				100	µs
T2.26.2	From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode				500	µs
100 Mb/s X1 TO TX_CLK TIMING (REFER TO Figure 5-27)⁽²⁶⁾
T2.27.1	X1 to TX_CLK delay	100 Mb/s Normal mode	0		5	ns

(1) In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84 ms.

(2) It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

(3) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(4) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(5) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(6) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.

(7) Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.

(8) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(9) 1 bit time = 10 ns in 100 Mb/s mode.

(10) PMD Input Pair voltage amplitude is greater than the Signal Detect Turnon Threshold Value.

(11) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(12) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK.

(13) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

(14) 1 bit time = 100 ns in 10 Mb/s mode.

(15) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV

(16) These specifications represent transmit timings.

(17) The signal amplitude on PMD Input Pair must be TP-PMD compliant.

(18) Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550 µs “dead-time”.

(19) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

(20) Per the RMII Specification, output delays assume a 25-pF load.

(21) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion.

(22) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.

(23) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

(24) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial deassertion of CRS_DV.

(25) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value (01).

(26) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.