9.2.1.1 Clock Requirements

DP83848 supports either an external CMOS-level oscillator source or a crystal resonator device. The X1 pin is the clock input, requiring either 25 or 50 MHz depending on the MII mode used. In MII mode (or RMII master mode in some products) either a 25-MHz crystal or 25-MHz oscillator may be used. For all PHYTER family products, the use of standard RMII mode (not RMII master mode) requires the use of a 50-MHz oscillator.

9.2.1.2 Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed, others may be compatible following the requirements listed in Table 60. TI recommends that the magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI.

9.2.2.1 TPI Network Circuit

Figure 41 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. The transmitter and the receiver of each node are DC isolated from the network cable by 1:1 transformers. A typical network configuration provides the services of autonegotiation, Auto-MDIX, 10-Mb/s operation, and 100-Mb/s operation. Autonegotiation is a feature which automatically determines the optimal network operating speed. Auto-MDIX is a feature allowing either straight-through or cross-over cables to be used. Autonegotiation uses link pulses to determine the operating mode. Link pulses appear as differential 2.5-V signals when ideal 50-Ω balanced loading is provided. 100 Mb/s data appears as 1 V, 0 V, and –1-V differential signals, and 10-Mb/s data appears as 2.5-V and –2.5-V differential signals across ideal loading. See Figure 44, Figure 45, and Figure 46.

Figure 41. Typical 10/100 Mb/s Twisted Pair Interface

9.2.2.2 Clock In (X1) Requirements

The DP83848 supports an external CMOS level oscillator source or a crystal resonator device.

9.2.2.2.2 Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 42 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance at cut crystal with a minimum drive level of 100 μW and a maximum of 500 μW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and CL2 should be set at 33 pF, and R1 should be set at 0 Ω.

Specification for 25 MHz crystal are listed in Table 63.

Figure 42. Crystal Oscillator Circuit

Table 61. 25-MHz Oscillator Specification

PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
Frequency			25		MHz
Frequency tolerance	Operational temperature			±50	ppm
Frequency stability	1 year aging			±50	ppm
Rise/Fall time	20% to 80%			6	ns
Jitter	Short term			800(1)	ps
Jitter	Long term			800(1)	ps
Symmetry	Duty cycle	40%		60%

(1) This limit is provided as a guideline for component selection and to ensure by production testing. Refer to AN-1548, PHYTER™ 100 Base-TX Reference Clock Jitter Tolerance, SNLA091 for details on jitter performance.

Table 62. 50 MHz Oscillator Specification

PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
Frequency			50		MHz
Frequency tolerance	Operational temperature			±50	ppm
Frequency stability	Operational temperature			±50	ppm
Rise/Fall time	20% - 80%			6	ns
Jitter	Short term			800(1)	ps
Jitter	Long term			800(1)	ps
Symmetry	Duty cycle	40%		60%

(1) This limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.

Table 63. 25 MHz Crystal Specification

PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
Frequency			25		MHz
Frequency tolerance	Operational temperature			±50	ppm
Frequency stability	1 year aging			±50	ppm
Load capacitance		25		40	pF

9.2.2.3 Power Feedback Circuit

To ensure correct operation for the DP83848, parallel caps with values of 10 μF (Tantalum) and 0.1 μF should be placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected to pin 23 (PFBOUT), each pin requires a small capacitor (.1 μF). See Figure 43 for proper connections.

Figure 43. Power Feedback Connection

9.2.2.4 Power Down and Interrupt

The power down and interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (0x11h) will configure the pin as an active low interrupt output.

9.2.2.5 Energy Detect Mode

When energy detect is enabled and there is no activity on the cable, the DP83848 will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848 to go through a normal power up sequence. Regardless of cable activity, the DP83848 will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy detect functionality is controlled via register energy detect control (EDCR), address 0x1Dh.