ZHCSC07E December 2013 – March 2019 DLPC2607
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Typical Current and Power Dissipation
- 6.6 I/O Characteristics
- 6.7 Internal Pullup and Pulldown Characteristics
- 6.8 Parallel I/F Frame Timing Requirements
- 6.9 Parallel I/F General Timing Requirements
- 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
- 6.11 BT.656 I/F General Timing Requirements
- 6.12 100- to 120-Hz Operational Limitations
- 6.13 Flash Interface Timing Requirements
- 6.14 DMD Interface Timing Requirements
- 6.15 mDDR Memory Interface Timing Requirements
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
-
10Layout
- 10.1
Layout Guidelines
- 10.1.1 Internal ASIC PLL Power
- 10.1.2 General Handling Guidelines for Unused CMOS-Type Pins
- 10.1.3 SPI Signal Routing
- 10.1.4 mDDR Memory and DMD Interface Considerations
- 10.1.5 PCB Design
- 10.1.6 General PCB Routing (Applies to All Corresponding PCB Signals)
- 10.1.7 Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
- 10.1.8 I/F Specific PCB Routing
- 10.1.9 Number of Layer Changes
- 10.1.10 Stubs
- 10.1.11 Termination Requirements:
- 10.2 Layout Example
- 10.1
Layout Guidelines
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- ZVB|176
散熱焊盤機械數據 (封裝 | 引腳)
8.2.2.1 Reference Clock
The device requires an external reference clock to feed its internal PLL. This reference may be supplied by a crystal or oscillator. For flexibility, the DLPC2607 device accepts either of two reference clock frequencies (see Table 5), but both must have a maximum frequency variation of 200 ppm (including aging, temperature, and trim component variation). When a crystal is used, the configuration requires several discrete components, as shown in Figure 11.
Figure 11. Recommended Crystal Oscillator Configuration Table 5. Crystal Port Characteristics
| PARAMETER | NOM | UNIT |
|---|---|---|
| PLL_REFCLK_I TO GND capacitance | 4.5 | pF |
| PLL_REFCLK_O TO GND capacitance | 4.5 | pF |
Table 6. Recommended Crystal Configuration
| PARAMETER | RECOMMENDED | UNIT |
|---|---|---|
| Crystal circuit configuration | Parallel resonant | |
| Crystal type | Fundamental (first harmonic) | |
| Crystal nominal frequency (See TSTPT_6 in the Pin Functions table) | 16.667 or 8.333 | MHz |
| Crystal frequency tolerance (including accuracy, temperature, aging, and trim sensitivity) | ±200 | PPM |
| Crystal drive level | 100 max | µW |
| Crystal equivalent series resistance (ESR) | 80 max | Ω |
| Crystal load | 12 | pF |
| RS drive resistor (nominal) | 100 | Ω |
| RFB feedback resistor (nominal) | 1 | MΩ |
| CL1 external crystal load capacitor | See Figure 11 | pF |
| CL2 external crystal load capacitor | See Figure 11 | pF |
| PCB layout | TI recommends a ground isolation ring around the crystal |
If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC2607 ASIC. Leave the PLL_REFCLK_O pins unconnected. An oscillator that provides a spread-spectrum clock reduces EMI.
NOTE
The DLPC2607 device accepts between 0% to –2% spreading (that is, down spreading only) with a modulation frequency between 20 kHz and 65 kHz and a triangular waveform.
Similar to the crystal option, the oscillator input frequency is limited to 16.667 or 8.333 MHz. To configure the DLPC2607 device to accept the 8.333-MHz reference clock option, an external pullup resistor to VCC18 must be applied to the TSTPT (6) pin. To configure the DLPC2607 device to accept the 16.667-MHz reference clock option, leave the TSTPT (6) pin unconnected.
It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.