ZHCSOO6C August 2000 – August 2021 DCV010505 , DCV010505D , DCV010512 , DCV010512D , DCV010515 , DCV010515D , DCV011512D , DCV011515D , DCV012405 , DCV012415D
PRODUCTION DATA
Due to the high power density of these devices, provide ground planes on the input and output.
Figure 11-1 shows a schematic for two DCV01 devices. Figure 11-2 and Figure 11-3 show a typical layout for two through-hole PDIP devices.
Input power and ground planes provide a low-impedance path for the input power. For the output, the COM signal connects through a ground plane, while the connections for the positive and negative voltage outputs conduct through wide traces to minimize losses.
The output must be taken from the device using ground and power planes, thereby ensuring minimum losses.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.
Allow the unused SYNC pin, to remain configured as a floating pad. It is advisable to place a guard ring (connected to input ground) or annulus connected around this pin to avoid any noise pickup. When connecting a SYNC pin to one or more SYNC design the linking trace to be short and narrow to avoid stray capacitance. Ensure that no other trace is in close proximity to this trace SYNC trace to decrease the stray capacitance on this pin. The stray capacitance affects the performance of the oscillator.