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ZHCSG81 April 2017 DCPA10505 , DCPA10505D , DCPA10512 , DCPA10512D , DCPA10515 , DCPA10515D

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

NVA|7
- MPDI058A
DUA|7
- MPDS097A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsg81_oa

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
Input voltage	+V_S		–0.5	6	V
	+V_S	50ns transient	–1.0	7	V
	SYNC_IN		–0.5	+V_S	V
	SYNC_IN	50ns transient	–1.0	6	V
Lead temperature (soldering, 10 s)				260	°C
Storage temperature, T_stg			–60	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Input voltage	4.5	5	5.5	V
Output power	0.05		1	W
Operating ambient temperature range	–40		100	°C

6.4 Electrical Characteristics

T_A = 25°C, +V_S = nominal, C_IN = 2.2 µF, C_OUT = 1.0 µF, (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
OUTPUT
P_OUT	Output power	Over +V_S range, I_OUT = 100% (full load)				1	W
I_OUT	Output current		DCPA10505			200	mA
			DCPA10505D			200⁽²⁾	mA
			DCPA10512			83	mA
			DCPA10512D			83⁽²⁾	mA
			DCPA10515			66	mA
			DCPA10515D			66⁽²⁾	mA
V_OUT	Output voltage	I_OUT = 100% load ⁽⁴⁾	DCPA10505		5.0		V
			DCPA10505D		±5.0		V
			DCPA10512		12.0		V
			DCPA10512D		±12.0		V
			DCPA10515		15.0		V
			DCPA10515D		±15.0		V
	Temperature variation	–40°C ≤ T_A ≤ 100°C, I_OUT = 100% load			0.02		%/°C
	Line regulation	+V_S(MIN) to +V_S(TYP), I_OUT = 10% load			10%
	Line regulation	+V_S(TYP) to +V_S(MAX), I_OUT = 10% load			10%
	Load regulation⁽¹⁾	10% to 100% load			5%
V_RIPPLE	Output voltage ripple⁽⁵⁾	C_OUT = 1 μF, I_OUT = 50%			20		mV_PP
INPUT
+V_S	Input voltage range			4.5		5.5	V
UVLO	+V_S Undervoltage lockout	+V_S increasing threshold				2.25	V
UVLO	+V_S Undervoltage lockout	+V_S decreasing threshold		1.7			V
I_Q	Quiescient current	I_OUT = 0% load	DCPA10505		35		mA
			DCPA10505D		25		mA
			DCPA10512		29		mA
			DCPA10512D		36		mA
			DCPA10515		31		mA
			DCPA10515D		38		mA
ISOLATION
V_ISO	Isolation	1-second flash test, voltage	DC	2.0⁽⁶⁾⁽⁵⁾			kVDC
		1-second flash test, voltage	AC	1.5⁽⁶⁾			kVrms
		1-second flash test, leakage current				30	µA
		Continuous working voltage across isolation barrier	DC			60	VDC
			AC			42.5	VAC
			dV/dt			50	V/ms
C_ISO	Barrier capacitance	V_ISO = 750 Vrms			28		pF
PERFORMANCE
	Efficiency	I_OUT = 100%	DCPA10505		85%
			DCPA10505D		85%
			DCPA10512		87%
			DCPA10512D		88%
			DCPA10515		86%
			DCPA10515D		86%
	Transient response⁽⁵⁾	50% to 100% load step	DCPA10505		3.0%
			DCPA10512		1.9%
			DCPA10515		2.0%
		50% to 100% load step per output⁽³⁾	DCPA10505D		2.7%
			DCPA10512D		2.0%
			DCPA10515D		1.6%
RELIABILITY
	Demonstrated	T_A = 55°C			55		FITS
CAPACITANCE
C_IN	External input capacitance	Ceramic		2.2			µF
C_OUT	External output capacitance	Ceramic		0.1	1.0	200	µF
THERMAL SHUTDOWN
T_SD	Die temperature at shutdown				168		°C
I_SD	Shutdown current				3		mA

(1) Load regulation = (V_OUT at 10% load – V_OUT at 100%)/V_OUT at 75% load

(2) I_OUT1 + I_OUT2

(3) Transient testing for dual output devices are tested with one output loaded with a 50% static load and the other output loaded with a 50% to 100% dynamic load step.

(4) See Load Regulation graphs in the Typical Characterization section for typical voltage at all load conditions.

(5) Guaranteed by design. Not production tested.

(6) See Isolation Voltage section for more information.

6.5 Switching Characteristics

at T_A = +25°C, +V_S = nominal, C_IN = 2.2 µF, C_OUT = 1.0 µF, (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OSC	Oscillator frequency	f_SW = f_OSC/2		850		kHz
f_SYNC	Synchronization frequency range		750		1000	kHz
V_IH	High-level input threshold, SYNC_IN		0.7			V
V_IL	Low-level input threshold, SYNC_IN				0.3	V

6.6 Typical Characteristics (DCPA10505)

At T_A = 25°C, +V_S = nominal, (unless otherwise noted)

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5Veff.gif

DCPA10505

Figure 1. Efficiency vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5Vloadreg.gif

DCPA10505

Figure 3. Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5Vripple2.gif

DCPA10505	COUT = 1 µF
	20-MHz BW

Figure 2. Output Ripple vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VlineReg2.gif

DCPA10505

Figure 4. Line Regulation

6.7 Typical Characteristics (DCPA10512)

At T_A = 25°C, +V_S = nominal, (unless otherwise noted)

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 12Veff.gif

DCPA10512

Figure 5. Efficiency vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 12VLoadReg.gif

DCPA10512

Figure 7. Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 12Vripple2.gif

DCPA10512	COUT = 1 µF
	20-MHz BW

Figure 6. Output Ripple vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 12VlineReg2.gif

DCPA10512

Figure 8. Line Regulation

6.8 Typical Characteristics (DCPA10515)

At T_A = 25°C, +V_S = nominal, (unless otherwise noted)

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15Veff.gif

DCPA10515

Figure 9. Efficiency vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15Vloadreg2.gif

DCPA10515

Figure 11. Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15Vripple2.gif

DCPA10515	COUT = 1 µF
	20-MHz BW

Figure 10. Output Ripple vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15Vlinereg.gif

DCPA10515

Figure 12. Line Regulation

6.9 Typical Characteristics (DCPA10505D)

At T_A = 25°C, +V_S = nominal, (unless otherwise noted)

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VDualEff.gif

DCPA10505D

Figure 13. Efficiency vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VDualposLoadReg.gif

DCPA10505D	+VOUT

Figure 15. +VOUT Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VDualnegLoadReg2.gif

DCPA10505D	–VOUT

Figure 17. –VOUT Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VDualripple2.gif

DCPA10505D	COUT = 1 µF
	20-MHz BW

Figure 14. Output Ripple vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VDualposLineReg2.gif

DCPA10505D	+VOUT

Figure 16. +VOUT Line Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 5VDualnegLineReg2.gif

DCPA10505D	–VOUT

Figure 18. –VOUT Line Regulation

6.10 Typical Characteristics (DCPA10512D)

At T_A = 25°C, +V_S = nominal, (unless otherwise noted)

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 12VDualEff.gif

DCPA10512D

Figure 19. Efficiency vs Load

DCPA10512D

+VOUT

Figure 21. +VOUT Load Regulation

DCPA10512D

–VOUT

Figure 23. –VOUT Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 12VDualripple2.gif

DCPA10512D	COUT = 1 µF
	20-MHz BW

Figure 20. Output Ripple vs Load

DCPA10512D

+VOUT

Figure 22. +VOUT Line Regulation

DCPA10512D

–VOUT

Figure 24. –VOUT Line Regulation

6.11 Typical Characteristics (DCPA10515D)

At T_A = 25°C, +V_S = nominal, (unless otherwise noted)

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15VDualEff.gif

DCPA10515D

Figure 25. Efficiency vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15VDualposLoadreg.gif

DCPA10515D	+VOUT

Figure 27. +VOUT Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15VDualnegLoadreg.gif

DCPA10515D	–VOUT

Figure 29. –VOUT Load Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15VDualripple2.gif

DCPA10515D	COUT = 1 µF
	20-MHz BW

Figure 26. Output Ripple vs Load

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15VDualposLinereg.gif

DCPA10515D	+VOUT

Figure 28. +VOUT Line Regulation

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D 15VDualnegLinereg2.gif

DCPA10515D	–VOUT

Figure 30. –VOUT Line Regulation