9.1.1.1 DC Characteristics

The DAC converts the 16-bit input code in the DACCODE registers to an equivalent current output. The ΣΔ DAC output is a current pulse which is then filtered by a third-order RC lowpass filter and boosted to produce the loop current (I_LOOP) at the device OUT pin.

Figure 15. Loop-Powered Transmitter

Figure 15 shows the principle of operation of the DAC161S997 in the Loop-Powered Transmitter (the circuit details are omitted for clarity). In Figure 15, I_D and I_A represent supply (quiescent) currents of the internal digital and analog blocks. I_AUX represents supply (quiescent) current of companion devices present in the system, such as the voltage regulator and the digital interface. Because both the control loop formed by the amplifier and the bipolar transistor force the voltage across R₁ and R₂ to be equal, under normal conditions, the I_LOOP is dependent only on I_DAC through the following relationship (see Equation 1).

Although I_Loop has a number of component currents, I_LOOP = I_DAC + I_D + I_A + I_AUX + I_E, only I_E is regulated by the loop to maintain the relationship shown in Equation 1. Because only the magnitude of I_E is controlled, not the direction, there is a lower limit to I_LOOP. This limit is dependent on the fixed components I_A and I_D, and on system implementation through I_AUX.

Figure 16. Self-Powered Transmitter

Figure 16 shows the variant of the transmitter where the local supply provides supply currents to the system blocks, and not the 4-20mA loop Self-Powered Transmitter. The ame basic relationship between the I_LOOP and I_DAC continues, but the component currents of I_LOOP are only I_DAC and I_E.

9.1.1.2 DC Input-Output Transfer Function

The output current sourced by the OUT pin of the device is expressed by Equation 2.

The valid DACCODE range is the full 16-bit code space (0x0000 to 0xFFFF), resulting in the I_DAC range of 0 to approximately 12 μA, which, however, does not result in the I_LOOP range of 0 to 24 mA. The maximum output current sourced out of OUT pin, I_LOOP, is 24 mA. The minimum output current is dependent on the system implementation. The minimum output current is the sum of the supply currents of the DAC161S997 internal blocks, I_A, I_D, and companion devices present in the system, I_AUX. The last component current, I_E, is theoretically controlled down to 0, however, due to the stability considerations of the control loop, not allowing the I_E to drop below 200 μA is advised.

The graph in Figure 17 shows the DC transfer characteristic of the 4-20mA transmitter, including minimum current limits. The minimum current limit for the Loop-Powered Transmitter is typically around 400 μA (I_D+ I_A + I_AUX + I_E). The minimum current limit for the Self-Powered Transmitter is typically around 200 μA (I_E). Typical values for I_D and I_A are listed in the Electrical Characteristics table. I_E depends on the BJT device used.

Figure 17. DAC-DC Transfer Function

9.1.1.3 Loop Interface

The DAC161S997 cannot directly interface to the typical 4 - 20 mA loop due to the excessive loop supply voltage. The loop interface has to provide the means of stepping down the LOOP Supply to 3.6V. This can be accomplished with either a linear regulator (LDO) or switching regulator while keeping in mind that the regulator’s quiescent current will have direct effect on the minimum achievable I_LOOP (see DC Input-Output Transfer Function).

The second component of the loop interface is the external NPN transistor (BJT). This device is part of the control circuit that regulates the transmitter’s output current (I_LOOP). Since the BJT operates over the wide current range, spanning at least 4 - 20 mA, it is necessary to degenerate the emitter in order to stabilize transistor’s transconductance (g_m). The degeneration resistor of 22Ω is suggested in typical applications. For circuit details, see Figure 21.

The NPN BJT should not be replaced with an N-channel FET (Field Effect Transistor) for the following reasons: discrete FET’s typically have high threshold voltages (VT), in the order of 1.5V to 2V, which is beyond the BASE output maximum range; discrete FET’s present higher load capacitance which may degrade system stability margins; and BASE output relies on the BJT’s base current for biasing.

9.1.1.4 Loop Compliance

The maximum V(LOOP+,LOOP-) potential is limited by the choice of step-down regulator, and the external BJT’s Collector Emitter breakdown voltage. For minimum V(LOOP+, LOOP−) potential consider TROUBLE Figure 16. Here, observe that V(LOOP+,LOOP−) ≅ min(V_CE) + I_LOOPR_E + I_LOOPR₂ = min(V_CE) + 0.53V + 0.96V = 3.66V, at I_LOOP = 24mA. The voltage drop across internal R₂ is specified in Electrical Characteristics.

9.1.1.5 AC Characteristics

The approximate frequency dependent characteristics of the loop drive circuit can be analyzed using the circuit in Figure 18.

Figure 18. Capacitances Affecting Control Loop

Here it is assumed that the internal amplifier dominates the frequency response of the system, and it has a single pole response. The BJT’s response, in the bandwidth of the control loop, is assumed to be frequency independent and is characterized by the transconductance g_m and the output resistance r_o.

As in previous sections I_DAC and I_AUX represent the filtered output of the ∑Δ modulator and the quiescent current of the companion devices.

The circuit in Figure 18 can be further simplified by omitting the on-board capacitances, whose effect will be discussed in Stability, and by combining the amplifier, the external transistor and resistor R_E into one G_m block. The resulting circuit is shown in Figure 19.

By assuming that the BJT’s output resistance (r_o) is large, the loop current I_LOOP can be expressed as:

Equation 3.

Figure 19. AC Analysis Model of a Transmitter

The sum of voltage drops around the path containing R₁, R₂ and v_e is:

Equation 4.

An assumption is made on the response of the internal amplifier:

Equation 5.

By combining the above the final expression for the I_LOOP as a function of 2 inputs I_DAC and I_AUX is:

Equation 6.

The result above reveals that there are 2 distinct paths from the inputs I_DAC and I_AUX to the output I_LOOP. I_DAC follows the low-pass, and the I_AUX follows the high-pass path.

In both cases the corner frequency is dependent on the effective transconductance, G_m, of the external transistor. This implies that control loop dynamics could vary with the output current I_LOOP if G_m were allowed to be just native device transconductance g_m. This undesirable behavior is mitigated by the degenerating resistor R_E which stabilizes G_m as follows:

Equation 7.

This results in the frequency response which is largely independent of the output current I_LOOP:

Equation 8.

While the bandwidth of the I_DAC path may not be of great consequence given the low frequency nature of the 4-20 mA current loop systems, the location of the pole in the I_AUX path directly affects PSRR of the transmitter circuit. This is further discussed in PSRR.

9.1.1.5.2 Output Impedance

The output impedance is described as:

Equation 9.

By considering the circuit in Figure 19, and setting I_DAC = I_AUX = 0, the following expression can be obtained:

Equation 10.

As in AC Characteristics an assumption can be made on the frequency response of the internal amplifier, and the effective transconductance G_m should be stabilized with external R_E leading to:

Equation 11.

The output impedance of the transmitter is a product of the external BJT's output resistance r_o, and the frequency characteristics of the internal amplifier. At low frequencies this results in a large impedance that does not significantly affect the output current accuracy.

9.1.1.5.3 PSRR

Power Supply Rejection Ratio is defined as the ability of the current control loop to reject the variations in the supply current of the companion devices, I_AUX. Specifically:

Equation 12.

It was shown in AC Characteristics that the I_AUX affects I_LOOP via the high-pass path whose corner frequency is dependent on the effective Gm of the external BJT. If that dependence were not mitigated with the degenerating resistor R_E, the PSRR would be degraded at low output current I_LOOP.

The typical PSRR performance of the transmitter shown in Figure 6 is shown in Typical Characteristics.

9.1.1.5.7 HART Signal Injection

The HART specification requires minimum suppression of the sensor signal in the HART signal band (1-2 kHz) of about 60 dB. The filter in Figure 20 below meets that requirement.

Figure 20. HART Signal Injection

9.2.2.1 Reasons for Choosing a 3.9-V Zener Diode

The first and most important requirement for the proper functioning of the entire circuitry is a stable power supply. A good design ensures that the LDO gets the sufficient input voltage (V_{IN_LDO}) to generate a stable 3.3 V under minimum-loop, power-supply voltage and minimum-loop current conditions.

From the circuit implementation, it is evident that the LDO input voltage V_{IN_LDO} is function of loop current and collector-emitter drop (V_CE ) of the bipolar junction transistor (BJT). Apply Kirchhoff ’ s Voltage Law (KVL) in the inner loop:

At minimum loop power supply voltage, BJT operation is pushed towards saturation, which means that V_CE is approximately 0 V (minimum). Due to the stability considerations of the current control loop, the minimum output current (I_LOOP(MIN)) below 200 μ A is not advised as shown in Figure 23.

To ensure stable 3.3-V LDO output under these conditions, the following relation must be fulfilled.

[(100 Ω × 200 μA)+ V_ZENER + 0 V + (20 Ω X 200 μA)] > 3.4 V

[V_ZENER + 0.024 V] > 3.4 V

From Equation 17, it is clear that without having a zener diode, a voltage greater than 3.4 V at the input of the LDO cannot be ensured. Therefore, choose a zener diode having a zener voltage (V_ZENER) greater than 3.4 V and able to handle power dissipation, P_DZ = V_ZENER × I_LOOP(MAX). In this application, the design uses a 3.9-V, 500-mW zener diode.

Figure 23. DAC DC Transfer Function

9.2.2.2 Loop Compliance Voltage

To calculate the minimum-loop, compliance-voltage (loop-power supply voltage), add all voltage drops in the loop at the maximum-expected loop current.

From a current control loop stability point of view, V_CE(MIN) must stay greater than maximum V_CE(SAT):

Applying Kirchhoff ’s Voltage Law in the outer loop, to find out the V_CE(MIN):

Rewriting Equation 19,

The maximum output current that can be sourced out of the OUT pin by DAC161S997, I LOOP (MAX) , is approximately 24 mA.

Figure 24. Series Voltage Drops in Current Loop System

Figure 25. Specification for Loop Current Output

Next, examine what NAMUR NE43 has to say about loop current. NAMUR NE43 is an international association of process instrumentation user companies that have worked on improving the diagnostic coverage in 4- to 20-mA analog output transmitters to address associated safety issues. NAMUR NE43 provides the guideline for signaling-failure information to the safety-interlock systems over a 4- to 20-mA loop. NAMUR NE43 recommends using 3.8 mA to 20.5 mA as an extended measurement information range. NAMUR NE43 recommends using loop current below 3.6 mA or above 21 mA is in the diagnostic failure information range. Choose I_LOOP(MAX) = 24 mA, depending upon DAC capability and also to comply with the NAMUR NE43 recommendation as shown in Figure 26.

Figure 26. NAMUR NE43 Recommendation

Rewriting Equation 20,

Figure 27 and Figure 28 give the loop supply voltages calculated using Equation 22 at different receiver load resistances and system wiring lengths.

Figure 27. Loop Power Supply Voltage for Different Loads and System Wiring Length in Feet

Figure 28. Loop Power Supply Voltage for Different Loads and System Wiring Length in Meter

However, the maximum loop compliance voltage must not exceed the absolute maximum voltage rating of any device used in the loop. Therefore, select the device in order to meet the maximum loop compliance voltage requirement

9.2.2.3 Selection of External BJT

DAC161S997 has been designed to use an external NPN transistor (BJT). Transistor Q1 conducts the majority of the signal-dependent, 4-20mA loop current. Using an external transistor avoids on-chip power dissipation and thermally-induced errors. Since the external transistor is part of a current control loop, the external transistor characteristics are not critical. Virtually any transistor with sufficient voltage, current and, power rating may be used. Basic requirements are as follows:

• V_CEO = 40 V minimum
• β = 40 minimum
• Must be able to handle power dissipation, P_D = V_CE(MAX) × I_LOOP(MAX)

The NPN BJT should not be replaced with an N-channel Field Effect Transistor (FET) for the following reasons. Discrete FET ’ s typically have high threshold voltages (V_TH), in the order of 1.5 V to 2 V, which is beyond the BASE output maximum range. Discrete FETs present higher load capacitance, which may degrade system stability margins. BASE output relies on the BJT’s base current for biasing.

For further information on a complete reference design of a Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter, refer to TIDU385A.