ZHCSVJ2I August   2007  – December 2024 CDCE937 , CDCEL937

PRODUCTION DATA  

1.   1
2. 1 特性
3. 2 應用
4. 3 說明
5. 4 Pin Configuration and Functions
6. 5 Specifications
   1. 5.1 Absolute Maximum Ratings
   2. 5.2 ESD Ratings
   3. 5.3 Recommended Operating Conditions
   4. 5.4 Thermal Information
   5. 5.5 Electrical Characteristics
   6. 5.6 Timing Requirements: CLK_IN
   7. 5.7 Timing Requirements: SDA/SCL
   8. 5.8 EEPROM Specification
   9. 5.9 Typical Characteristics
7. 6 Parameter Measurement Information
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
   4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
   5. 7.5 Programming
9. 8 Register Maps
   1. 8.1 SDA/SCL Configuration Registers
10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
       1. 9.2.1 Design Requirements
       2. 9.2.2 Detailed Design Procedure
          1. 9.2.2.1 Spread Spectrum Clock (SSC)
          2. 9.2.2.2 PLL Frequency Planning
          3. 9.2.2.3 Crystal Oscillator Start-Up
          4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
          5. 9.2.2.5 Unused Inputs and Outputs
          6. 9.2.2.6 Switching Between XO and VCXO Mode
       3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
       1. 9.4.1 Layout Guidelines
       2. 9.4.2 Layout Example
11. 10Device and Documentation Support
    1. 10.1 Device Support
       1. 10.1.1 第三方產品免責聲明
       2. 10.1.2 Development Support
    2. 10.2 Documentation Support
       1. 10.2.1 Related Documentation
    3. 10.3 接收文檔更新通知
    4. 10.4 支持資源
    5. 10.5 Trademarks
    6. 10.6 靜電放電警告
    7. 10.7 術語表
12. 11Revision History
13. 12Mechanical, Packaging, and Orderable Information