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SCAS862G November 2008 – July 2016 CDCE62005

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND131R

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage range⁽²⁾	–0.5	4.6	V
V_I	Input voltage range⁽³⁾	–0.5	VCC + 0.5	V
V_O	Output voltage range⁽³⁾	–0.5	VCC + 0.5	V
	Input Current (V_I < 0, V_I > V_CC)		±20	mA
	Output current for LVPECL/LVCMOS Outputs (0 < V_O < V_CC)		±50	mA
T_J	Junction temperature		125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All supply voltages have to be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.

6.2 ESD Ratings

			MIN	MAX	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Thermal Information⁽²⁾⁽³⁾

THERMAL METRIC⁽¹⁾		RGZ	UNIT
THERMAL METRIC⁽¹⁾		48 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	28.9⁽⁵⁾	°C/W
		20.4⁽⁶⁾
		27.3⁽⁷⁾
		20.3⁽⁸⁾
R_θJC(top)	Junction-to-case (top) thermal resistance	12.9	°C/W
R_θJB	Junction-to-board thermal resistance	4.0	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	4.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W
θ_JP	Junction-to-pad⁽⁴⁾	2⁽⁵⁾	°C/W
		2⁽⁶⁾
		2⁽⁷⁾
		2⁽⁸⁾

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(3) Connected to GND with 36 thermal vias (0,3 mm diameter).

(4) θ_JP (Junction – Pad) is used for the QFN Package, because the main heat flow is from the Junction to the GND-Pad of the QFN.

(5) JEDEC Compliant Board (6X6 VIAs on PAD), Ariflow = 0 LFM

(6) JEDEC Compliant Board (6X6 VIAs on PAD) , Airflow = 100 LFM

(7) Recommended Layout (7X7 VIAs on PAD), Airflow = 0 LFM

(8) Recommended Layout (7X7 VIAs on PAD), Airflow = 100 LFM

6.4 Electrical Characteristics

recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C to 85°C

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
POWER SUPPLY
V_CC	Supply voltage			3	3.3	3.6	V
V_{CC_PLL}, V_{CC_IN}, V_{CC_VCO}, V_CCA	Analog supply voltage			3	3.3	3.6
P_LVPECL	REF at 30.72,MHz, Outputs are LVPECL	Output 1 = 491.52 MHz Output 2 = 245.76 MHz Output 3 = 122.88 MHz Output 4 = 61.44 MHz Output 5 = 30.72 MHz In case of LVCMOS Output1 = 245.76 MHz			1.9		W
P_LVDS	REF at 30.72 MHz, Outputs are LVDS				1.65		W
P_LVCMOS	REF at 30.72 MHz, Outputs are LVCMOS				1.8		W
P_OFF	REF at 30.72 MHz	Dividers are disabled. Outputs are disabled.			0.75		W
P_PD		Device is powered down			20		mW
DIFFERENTIAL INPUT MODE (PRI_REF, SEC_REF)
V_IN	Differential input amplitude (V_IN – V_/IN)			0.1		1.3	V
V_IC	Common-mode input voltage			1.0		V_CC–0.3	V
I_IH	Differential input current high (no internal termination)	V_I = V_CC, V_CC = 3.6 V				20	μA
I_IL	Differential input current low (no internal termination)	V_I = 0 V, V_CC = 3.6 V		–20		20	μA
	Input Capacitance on PRI_REF, SEC_REF				3		pF
CRYSTAL INPUT SPECIFICATIONS
	On-chip load capacitance				10		pF
	Equivalent series resistance (ESR)					50	Ω
LVCMOS INPUT MODE (SPI_CLK, SPI_MOSI, SPI_LE, Power_Down, SYNC, REF_SEL, PRI_REF, SEC_REF )
	Low-level input voltage LVCMOS,			0		0.3 x V_CC	V
	High-level input voltage LVCMOS			0.7 x V_CC		V_CC	V
V_IK	LVCMOS input clamp voltage	V_CC = 3 V, I_I = –18 mA				–1.2	V
I_IH	LVCMOS input current	V_I= V_CC, V_CC = 3.6 V				20	μA
I_IL	LVCMOS input (Except PRI_REF and SEC_REF)	V_I = 0 V, V_CC = 3.6 V		–10		–40	μA
I_IL	LVCMOS input (PRI_REF and SEC_REF)	V_I = 0 V, V_CC = 3.6 V		–10		10	μA
C_I	Input capacitance	V_I = 0 V or V_CC			3		pF
SPI OUTPUT (MISO) / PLL_LOCK OUTPUT
I_OH	High-level output current	V_CC = 3.3 V,	V_O = 1.65 V		–30		mA
I_OL	Low-level output current	V_CC = 3.3 V,	V_O = 1.65 V		33		mA
V_OH	High-level output voltage for LVCMOS outputs	V_CC = 3 V,	I_OH = −100 μA	V_CC–0.5			V
V_OL	Low-level output voltage for LVCMOS outputs	V_CC = 3 V,	I_OL = 100 μA			0.3	V
C_O	Output capacitance on MISO	VCC = 3.3 V; VO = 0 V or VCC⁽¹⁾			3		pF
I_OZH	3-state output current	V_O = V_CC V_O = 0 V			5		μA
I_OZL	3-state output current	V_O = V_CC V_O = 0 V			–5		μA
EEPROM
EEcy	Programming cycle of EEPROM			100	1000		Cycles
EEret	Data retention			10			Years
VBB
VBB	Termination voltage for reference inputs.	I_BB = –0.2 mA, Depending on the setting.		0.9		1.9	V
INPUT BUFFERS INTERNAL TERMINATION RESISTORS (PRI_REF and SEC_REF)
	Termination resistance	Single ended			50		Ω
PHASE DETECTOR
f_CPmax	Charge pump frequency			0.04		40	MHz
LVCMOS OUTPUT / AUXILIARY OUTPUT⁽¹⁾
f_clk	Output frequency (see Figure 7)	Load = 5 pF to GND		0		250	MHz
V_OH	High-level output voltage for LVCMOS outputs	V_CC = min to max	I_OH = –100 μA	V_CC –0.5
V_OL	Low-level output voltage for LVCMOS outputs	V_CC = min to max	I_OL =100 µA			0.3	V
I_OH	High-level output current	V_CC = 3.3 V	V_O = 1.65 V		–30		mA
I_OL	Low-level output current	V_CC = 3.3 V	V_O = 1.65 V		33		mA
t_pho	Reference (PRI_REF or SEC_REF) to Output Phase offset	Outputs are set to 122.88 MHz, Reference at 30.72 MHz			0.35		ns
t_pd(LH)/ t_pd(HL)	Propagation delay from PRI_REF or SEC_REF to Outputs	Crosspoint to V_CC/2, Bypass Mode			4		ns
t_sk(o)	Skew, output to output For Y0 to Y4	All Outputs set at 200 MHz, Reference = 200 MHz			75		ps
C_O	Output capacitance on Y0 to Y4	V_CC = 3.3 V; V_O = 0 V or V_CC			5		pF
I_OZH	3-State LVCMOS output current	V_O = V_CC			5		μA
I_OZL	3-State LVCMOS output current	V_O = 0 V			–5		μA
I_OPDH	Power Down output current	V_O = V_CC				25	μA
I_OPDL	Power Down output current	V_O = 0 V				5	μA
	Duty cycle LVCMOS			45%		55%
t_slew-rate	Output rise/fall slew rate			3.6	5.2		V/ns
LVDS OUTPUT⁽¹⁾⁽³⁾
f_clk	Output frequency (see Figure 8)	Configuration Load		0		800	MHz
\|V_OD\|	Differential output voltage	R_L = 100 Ω		270		550	mV
ΔV_OD	LVDS VOD magnitude change					50	mV
	Offset Voltage	40°C to 85°C			1.24		V
ΔV_OS	VOS magnitude change				40		mV
	Short circuit Vout+ to ground	VOUT = 0				27	mA
	Short circuit Vout– to ground	VOUT = 0				27	mA
t_pho	Reference (PRI_REF or SEC_REF) to output phase offset	Outputs are set to 491.52 MHz Reference at 30.72 MHz			1.65		ns
t_pd(LH)/t_pd(HL)	Propagation delay from PRI_REF or SEC_REF to outputs	Crosspoint to Crosspoint, Bypass Mode			3.1		ns
t_sk(o)⁽²⁾	Skew, output to output For Y0 to Y4	All Outputs set at 200 MHz			25		ps
C_O	Output capacitance on Y0 to Y4	V_CC= 3.3 V; V_O = 0 V or V_CC			5		pF
I_OPDH	Power down output current	V_O = V_CC				25	μA
I_OPDL	Power down output current	V_O = 0 V				5	μA
	Duty cycle			45%		55%
t_r / t_f	Rise and fall time	20% to 80% of V_OUT(PP)		110	160	190	ps
LVCMOS-TO-LVDS⁽⁴⁾
t_{skP_c}	Output skew between LVCMOS and LVDS outputs	V_CC/2 to Crosspoint. Output are at the same output frequency and use the same output divider configuration.		0.9	1.4	1.9	ns
LVPECL OUTPUT
f_clk	Output frequency, Configuration load (see Figure 9 and Figure 10)			0		1500	MHz
V_OH	LVPECL high-level output voltage load			V_CC –1.06		V_CC –0.88	V
V_OL	LVPECL low-level output voltage load			V_CC–2.02		V_CC–1.58	V
\|V_OD\|	Differential output voltage			610		970	mV
t_pho	Reference to Output Phase offset	Outputs are set to 491.52 MHz, Reference at 30.72 MHz			1.47		ns
t_pd(LH)/ t_pd(HL)	Propagation delay from PRI_REF or SEC_REF to outputs	Crosspoint to Crosspoint, Bypass Mode			3.4		ns
t_sk(o)	Skew, output to output For Y0 to Y4	All Outputs set at 200 MHz			25		ps
C_O	Output capacitance on Y0 to Y4	V_CC = 3.3 V; V_O = 0 V or V_CC			5		pF
I_OPDH	Power Down output current	V_O = V_CC				25	μA
I_OPDL	Power Down output current	V_O = 0 V				5	μA
	Duty Cycle			45%		55%
t_r / t_f	Rise and fall time	20% to 80% of V_OUT(PP)		55	75	135	ps
LVDS-TO-LVPECL
t_{skP_C}	Output skew between LVDS and LVPECL outputs	Crosspoint to Crosspoint output dividers are configured identically.		0.9	1.1	1.3	ns
LVCMOS-TO-LVPECL
t_{skP_C}	Output skew between LVCMOS and LVPECL outputs	V_CC/2 to Crosspoint output dividers are configured identically.		–150	260	700	ps
LVPECL HI-SWING OUTPUT
V_OH	LVPECL high-level output voltage load			V_CC –1.11		V_CC –0.87	V
V_OL	LVPECL low-level output voltage load			V_CC –2.06		V_CC –1.73	V
\|V_OD\|	Differential output voltage			760		1160	mV
t_r / t_f	Rise and fall time	20% to 80% of V_OUT(PP)		55	75	135	ps

(1) All typical values are at V_CC = 3.3 V, temperature = 25°C

(2) The t_sk(o) specification is only valid for equal loading of all outputs.

(3) The phase of LVCMOS is lagging in reference to the phase of LVDS.

(4) All typical values are at V_CC = 3.3 V, temperature = 25°C

6.5 Timing Requirements

over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted)

		MIN	MAX	UNIT
PRI_REF/SEC_REF REQUIREMENTS
f_max	Maximum Clock Frequency Applied to PRI_REF and SEC_REF in fan-out mode		1500	MHz
	Maximum Clock Frequency Applied to Smart Multiplexer input Divider		500	MHz
	Maximum Clock Frequency Applied to Reference Divider		250	MHz
	For Single ended Inputs ( LVCMOS) on PRI_REF and SEC_REF		250	MHz
	Duty cycle of PRI_REF or SEC_REF at V_CC/ 2	40%	60%
	Input Clock Slew Rate (Differential and Single ended)	1		V/ns
Power_Down, SYNC, REF_SEL REQUIREMENTS
t_r/ t_f	Rise and fall time of the Power_Down, SYNC, REF_SEL signal from 20% to 80% of V_CC		4	ns

6.6 SPI Bus Timing Characteristics

			MIN	MAX	UNIT
f_Clock	Clock Frequency for the SPI_CLK			20	MHz
t₁	SPI_LE to SPI_CLK setup time	See Figure 1 and Figure 2	10		ns
t₂	SPI_MOSI to SPI_CLK setup time	See Figure 1 and Figure 2	10		ns
t₃	SPI_MOSI to SPI_CLK hold time	See Figure 1 and Figure 2	10		ns
t₄	SPI_CLK high duration	See Figure 1 and Figure 2	25		ns
t₅	SPI_CLK low duration	See Figure 1 and Figure 2	25		ns
t₆	SPI_CLK to SPI_LE Hold time	See Figure 1 and Figure 2	10		ns
t₇	SPI_LE Pulse Width	See Figure 1 and Figure 2	20		ns
t₈	SPI_CLK to MISO data valid	See Figure 2		10	ns
t₉	SPI_LE to SPI_MISO Data Valid	See Figure 2		10	ns