ZHCSKT0J November 1998 – August 2024 CD4066B
PRODUCTION DATA
7.2 Functional Block Diagram
A. All control inputs are protected by the CMOS protection network.
B. All p substrates are connected to VDD.
C. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS.
D. Signal-level range: VSS ≤ Vis ≤ VDD.
Figure 7-1 Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry