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ZHCS896I May 2009 – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RGC|64
- MPQF125F

散熱焊盤機械數據 (封裝 | 引腳)

RGC|64
- QFND102O

訂購信息

6.10.4 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins of ports P1 through P3 (see Table 6-6). Table 6-7 lists the default settings for all pins that support port mapping.

Table 6-6 Port Mapping, Mnemonics and Functions

VALUE	PxMAPy MNEMONIC	INPUT PIN FUNCTION (PxDIR.y = 0)	OUTPUT PIN FUNCTION (PxDIR.y = 1)
0	PM_NONE	None	DVSS
1⁽¹⁾	PM_CBOUT0	–	Comparator_B output (on TA0 clock input)
1⁽¹⁾	PM_TA0CLK	TA0 clock input	–
2⁽¹⁾	PM_CBOUT1	–	Comparator_B output (on TA1 clock input)
2⁽¹⁾	PM_TA1CLK	TA1 clock input	–
3	PM_ACLK	None	ACLK output
4	PM_MCLK	None	MCLK output
5	PM_SMCLK	None	SMCLK output
6	PM_RTCCLK	None	RTCCLK output
7⁽¹⁾	PM_ADC12CLK	–	ADC12CLK output
7⁽¹⁾	PM_DMAE0	DMA external trigger input	–
8	PM_SVMOUT	None	SVM output
9	PM_TA0CCR0A	TA0 CCR0 capture input CCI0A	TA0 CCR0 compare output Out0
10	PM_TA0CCR1A	TA0 CCR1 capture input CCI1A	TA0 CCR1 compare output Out1
11	PM_TA0CCR2A	TA0 CCR2 capture input CCI2A	TA0 CCR2 compare output Out2
12	PM_TA0CCR3A	TA0 CCR3 capture input CCI3A	TA0 CCR3 compare output Out3
13	PM_TA0CCR4A	TA0 CCR4 capture input CCI4A	TA0 CCR4 compare output Out4
14	PM_TA1CCR0A	TA1 CCR0 capture input CCI0A	TA1 CCR0 compare output Out0
15	PM_TA1CCR1A	TA1 CCR1 capture input CCI1A	TA1 CCR1 compare output Out1
16	PM_TA1CCR2A	TA1 CCR2 capture input CCI2A	TA1 CCR2 compare output Out2
17⁽²⁾	PM_UCA0RXD	USCI_A0 UART RXD (direction controlled by USCI – input)
17⁽²⁾	PM_UCA0SOMI	USCI_A0 SPI slave out master in (direction controlled by USCI)
18⁽²⁾	PM_UCA0TXD	USCI_A0 UART TXD (direction controlled by USCI – output)
18⁽²⁾	PM_UCA0SIMO	USCI_A0 SPI slave in master out (direction controlled by USCI)
19⁽³⁾	PM_UCA0CLK	USCI_A0 clock input/output (direction controlled by USCI)
19⁽³⁾	PM_UCB0STE	USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
20⁽⁴⁾	PM_UCB0SOMI	USCI_B0 SPI slave out master in (direction controlled by USCI)
20⁽⁴⁾	PM_UCB0SCL	USCI_B0 I²C clock (open drain and direction controlled by USCI)
21⁽⁴⁾	PM_UCB0SIMO	USCI_B0 SPI slave in master out (direction controlled by USCI)
21⁽⁴⁾	PM_UCB0SDA	USCI_B0 I²C data (open drain and direction controlled by USCI)
22⁽⁵⁾	PM_UCB0CLK	USCI_B0 clock input/output (direction controlled by USCI)
22⁽⁵⁾	PM_UCA0STE	USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
23	PM_RFGDO0	Radio GDO0 (direction controlled by Radio)
24	PM_RFGDO1	Radio GDO1 (direction controlled by Radio)
25	PM_RFGDO2	Radio GDO2 (direction controlled by Radio)
26	Reserved	None	DVSS
27	Reserved	None	DVSS
28	Reserved	None	DVSS
29	Reserved	None	DVSS
30	Reserved	None	DVSS
31 (0FFh)⁽⁶⁾	PM_ANALOG	Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.

(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR.

(2) UART or SPI functionality is determined by the selected USCI mode.

(3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode even if 4-wire mode is selected.

(4) SPI or I²C functionality is determined by the selected USCI mode. In case the I²C functionality is selected the output of the mapped pin drives only the logical 0 to V_SS level.

(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode even if 4-wire mode is selected.

(6) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored, resulting in a read value of 31.

Table 6-7 Default Mapping

PIN	PxMAPy MNEMONIC	INPUT PIN FUNCTION (PxDIR.y = 0)	OUTPUT PIN FUNCTION (PxDIR.y = 1)
P1.0/P1MAP0	PM_RFGDO0	None	Radio GDO0
P1.1/P1MAP1	PM_RFGDO2	None	Radio GDO2
P1.2/P1MAP2	PM_UCB0SOMI/PM_UCB0SCL	USCI_B0 SPI slave out master in (direction controlled by USCI), USCI_B0 I²C clock (open drain and direction controlled by USCI)
P1.3/P1MAP3	PM_UCB0SIMO/PM_UCB0SDA	USCI_B0 SPI slave in master out (direction controlled by USCI), USCI_B0 I²C data (open drain and direction controlled by USCI)
P1.4/P1MAP4	PM_UCB0CLK/PM_UCA0STE	USCI_B0 clock input/output (direction controlled by USCI), USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P1.5/P1MAP5	PM_UCA0RXD/PM_UCA0SOMI	USCI_A0 UART RXD (direction controlled by USCI – input), USCI_A0 SPI slave out master in (direction controlled by USCI)
P1.6/P1MAP6	PM_UCA0TXD/PM_UCA0SIMO	USCI_A0 UART TXD (direction controlled by USCI – output), USCI_A0 SPI slave in master out (direction controlled by USCI)
P1.7/P1MAP7	PM_UCA0CLK/PM_UCB0STE	USCI_A0 clock input/output (direction controlled by USCI), USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
P2.0/P2MAP0	PM_CBOUT1/PM_TA1CLK	TA1 clock input	Comparator_B output
P2.1/P2MAP1	PM_TA1CCR0A	TA1 CCR0 capture input CCI0A	TA1 CCR0 compare output Out0
P2.2/P2MAP2	PM_TA1CCR1A	TA1 CCR1 capture input CCI1A	TA1 CCR1 compare output Out1
P2.3/P2MAP3	PM_TA1CCR2A	TA1 CCR2 capture input CCI2A	TA1 CCR2 compare output Out2
P2.4/P2MAP4	PM_RTCCLK	None	RTCCLK output
P2.5/P2MAP5	PM_SVMOUT	None	SVM output
P2.6/P2MAP6	PM_ACLK	None	ACLK output
P2.7/P2MAP7	PM_ADC12CLK/PM_DMAE0	DMA external trigger input	ADC12CLK output
P3.0/P3MAP0	PM_CBOUT0/PM_TA0CLK	TA0 clock input	Comparator_B output
P3.1/P3MAP1	PM_TA0CCR0A	TA0 CCR0 capture input CCI0A	TA0 CCR0 compare output Out0
P3.2/P3MAP2	PM_TA0CCR1A	TA0 CCR1 capture input CCI1A	TA0 CCR1 compare output Out1
P3.3/P3MAP3	PM_TA0CCR2A	TA0 CCR2 capture input CCI2A	TA0 CCR2 compare output Out2
P3.4/P3MAP4	PM_TA0CCR3A	TA0 CCR3 capture input CCI3A	TA0 CCR3 compare output Out3
P3.5/P3MAP5	PM_TA0CCR4A	TA0 CCR4 capture input CCI4A	TA0 CCR4 compare output Out4
P3.6/P3MAP6	PM_RFGDO1	None	Radio GDO1
P3.7/P3MAP7	PM_SMCLK	None	SMCLK output