5.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios

5.3.2.2 Current Consumption for Different LE Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10-dBm output power

5.5.1.1 Power Sources

The CC256x device requires two power sources:

• VDD_IN: main power supply for the device
• VDD_IO: power source for the 1.8-V I/O ring

The HCI module includes several on-chip voltage regulators for increased noise immunity and can be connected directly to the battery.

5.5.1.2 Device Power-Up and Power-Down Sequencing

The device includes the following power-up requirements (see Figure 5-1):

• nSHUTD must be low. VDD_IN and VDD_IO are don't-care when nSHUTD is low. However, signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe. Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages with no VDD_IO and VDD_IN.
• VDD_IO and VDD_IN must be stable before releasing nSHUTD.
• The fast clock must be stable within 20 ms of nSHUTD going high.
• The slow clock must be stable within 2 ms of nSHUTD going high.

The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to 100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case, ensure that the sequence and requirements are met.

Figure 5-1 Power-Up and Power-Down Sequence

5.5.1.3 Power Supplies and Shutdown – Static States

The nSHUTD signal puts the device in ultra-low power mode and performs an internal reset to the device. The rise time for nSHUTD must not exceed 20 μs; nSHUTD must be low for a minimum of 5 ms.

To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in Section 4.1, Pin Attributes. Table 5-1 describes the static operation states.

5.5.1.4 I/O States in Various Power Modes

Table 5-2 lists the I/O states in various power modes.

5.5.1.5 nSHUTD Requirements

5.5.2.1 Slow Clock Requirements

An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The accuracy of the slow clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD.

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5.5.2.2 External Fast Clock Crystal Requirements and Operation

5.5.2.3 Fast Clock Source Requirements (–40°C to +85°C)

5.5.3.1 UART

Figure 5-2 shows the UART timing diagram.

Figure 5-2 UART Timing

Table 5-3 lists the UART timing characteristics.

Figure 5-3 shows the UART data frame.

Figure 5-3 Data Frame

Table 5-4 describes the symbols used in Figure 5-3.

5.5.3.2 PCM

Figure 5-4 shows the interface timing for the PCM.

Figure 5-4 PCM Interface Timing

Table 5-5 lists the associated PCM master parameters.

Table 5-6 lists the associated PCM slave parameters.

5.5.4.1 Bluetooth BR/EDR RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port.

5.5.4.2 Bluetooth LE RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port.