SWRS037B January 2006 – March 2015 CC1150
PRODUCTION DATA.
- 1Device Overview
- 2Revision History
- 3Terminal Configuration and Functions
-
4Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 ESD Ratings
- 4.3 Recommended Operating Conditions
- 4.4 General Characteristics
- 4.5 Current Consumption
- 4.6 RF Transmit
- 4.7 Crystal Oscillator
- 4.8 Frequency Synthesizer Characteristics
- 4.9 Analog Temperature Sensor
- 4.10 DC Characteristics
- 4.11 Power-On Reset
- 4.12 Thermal Resistance Characteristics for VQFNP Package
-
5Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3 Configuration Overview
- 5.4 Configuration Software
- 5.5 4-wire Serial Configuration and Data Interface
- 5.6 Microcontroller Interface and Pin Configuration
- 5.7 Data Rate Programming
- 5.8 Packet Handling Hardware Support
- 5.9 Modulation Formats
- 5.10 Forward Error Correction with Interleaving
- 5.11 Radio Control
- 5.12 Data FIFO
- 5.13 Frequency Programming
- 5.14 VCO
- 5.15 Voltage Regulators
- 5.16 Output Power Programming
- 5.17 General Purpose and Test Output Control Pins
- 5.18 Asynchronous and Synchronous Serial Operation
- 5.19 System Considerations and Guidelines
- 5.20 Memory
- 6Applications, Implementation, and Layout
- 7Device and Documentation Support
- 8Mechanical Packaging and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGV|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGV|16
訂購信息
6 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Typical Application
A simplified block diagram of CC1150 is shown in Figure 5-1.
Only a few external components are required for using the CC1150. The recommended application circuits are shown in Figure 6-1 and Figure 6-2. The external components are described in Table 6-1, and typical values are given in Table 6-2.
Figure 6-1 Typical Application and Evaluation Circuit 315/433 MHz (Excluding Supply Decoupling Capacitors)
Figure 6-2 Typical Application and Evaluation Circuit 868/915 MHz(Excluding Supply Decoupling Capacitors)
Table 6-1 Overview of External Components (Excluding Supply Decoupling Capacitors)
| COMPONENT | DESCRIPTION |
|---|---|
| C41 | Decoupling capacitor for on-chip voltage regulator to digital part |
| C51/C71 | Crystal loading capacitors |
| C101/C111 | RF balun/matching capacitors |
| C102 | RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz). |
| C103 | RF LC filter/matching capacitors |
| C104 | RF balun DC blocking capacitor |
| C105 | RF LC filter DC blocking capacitor and part of optional RF LC filter (868/915 MHz) |
| C106 | Part of optional RF LC filter and DC Block (868/915 MHz) |
| L101/L111 | RF balun/matching inductors (inexpensive multi-layer type) |
| L102 | RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz) (inexpensive multi-layer type) |
| L103 | RF LC filter/matching inductor (inexpensive multi-layer type) |
| L104 | RF LC filter/matching inductor (inexpensive multi-layer type) |
| L105 | Part of optional RF LC filter (868/915 MHz)(inexpensive multi-layer type) |
| R141 | Resistor for internal bias current reference |
| XTAL | 26 to 27 MHz crystal |
Table 6-2 Bill of Materials for the Application Circuit(1)
| COMPONENT | VALUE @ 31 5MHz | VALUE @ 433 MHz | VALUE @ 868/915 MHz |
|---|---|---|---|
| C41 | 100 nF ± 10%, 0402 X5R | ||
| C51 | 27 pF ± 5%, 0402 NP0 | ||
| C71 | 27 pF ± 5%, 0402 NP0 | ||
| C101 | 6.8 pF ± 0.5 pF, 0402 NP0 | 3.9 pF ± 0.25 pF, 0402 NP0 | 1.0 pF ± 0.25 pF, 0402 NP0 |
| C102 | 12 pF ± 5%, 0402 NP0 | 8.2 pF ± 0.5 pF, 0402 NP0 | 1.5 pF ± 0.25 pF, 0402 NP0 |
| C103 | 6.8 pF ± 0.5 pF, 0402 NP0 | 5.6 pF ± 0.5pF, 0402 NP0 | 3.3 pF ± 0.25 pF, 0402 NP0 |
| C104 | 220 pF ± 5%, 0402 NP0 | 220 pF ± 5%, 0402 NP0 | 100 pF ± 5%, 0402 NP0 |
| C105 | 220 pF ± 5%, 0402 NP0 | 220 pF ± 5%, 0402 NP0 | 100 pF ± 5%, 0402 NP0 (12 pF ± 5%, 0402 NP0 if optionally 699 MHz filter is desired) |
| C106 | (47 pF ± 5%, 0402 NP0 if optionally 699 MHz filter is desired) |
||
| C111 | 6.8 pF ± 0.5 pF, 0402 NP0 | 3.9 pF ± 0.25 pF, 0402 NP0 | 1.5 pF ± 0.25pF, 0402 NP0 |
| L101 | 33 nH ± 5%, 0402 monolithic | 27 nH ± 5%, 0402 monolithic | 12 nH ± 5%, 0402 monolithic |
| L102 | 18 nH ± 5%, 0402 monolithic | 22 nH ± 5%, 0402 monolithic | 18 nH ± 5%, 0402 monolithic |
| L103 | 33 nH ± 5%, 0402 monolithic | 27 nH ± 5%, 0402 monolithic | 12 nH ± 5%, 0402 monolithic |
| L104 | (12 nH ± 5%, 0402 monolithic if optionally 699 MHz filter is desired) | ||
| L105 | 3.3 nH ± 5%, 0402 monolithic | ||
| L111 | 33 nH ± 5%, 0402 monolithic | 27 nH ± 5%, 0402 monolithic | 12 nH ± 5%, 0402 monolithic |
| L112 | 18 nH ± 5%, 0402 monolithic | ||
| R141 | 56 kΩ ±1%, 0402 | ||
| XTAL | 26.0 MHz surface mount crystal | ||
6.2 Design Requirements
6.2.1 Bias Resistor
The bias resistor R141 is used to set an accurate bias current.
6.2.2 Balun and RF Matching
The components between the RF_N/RF_P pins and the point where the two signals are joined together [(C111, C101, L101 and L111 for the 315/433 MHz design) and (L101, L111, C101, L102, C111, C102 and L112 for the 868/915 MHz reference design)] form a balun that converts the differential RF signal on CC1150 to a single-ended RF signal. C104 is needed for dc blocking. Together with an appropriate LC filter network, the balun components also transform the impedance to match a 50-Ω antenna (or cable). C105 provides dc blocking and is only needed if there is a dc path in the antenna. For the 868/915 MHz reference design, this component may also be used for additional filtering, see Section 6.2.5.
Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in Table 6-2.
The balun and LC filter component values and their placement are important to achieve optimal performance. It is highly recommended to follow the CC1150EM reference design (see [1] and [2]). Gerber files and schematics for the reference designs are available for download from CC1150EM433 and CC1150EM868.
6.2.3 Crystal
A crystal in the frequency range of 26 to 27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C51 and C71) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL , specified for the crystal. The total load capacitance seen between the crystal terminals should equal CL for the crystal to oscillate at the specified frequency.
The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF.
The crystal oscillator circuit is shown in Figure 6-3. Typical component values for different values of CL are given in Table 6-3.
Figure 6-3 Crystal Oscillator Circuit
The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start up (see Section 4.7).
The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application.
Table 6-3 Crystal Oscillator Component Values
| COMPONENT | CL= 10 pF | CL= 13 pF | CL= 16 pF |
|---|---|---|---|
| C51 | 15 pF | 22 pF | 27 pF |
| C71 | 15 pF | 22 pF | 27 pF |
6.2.4 Reference Signal
The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a full-swing digital signal (0 V to VDD) or a sine wave of maximum 1-V peak-to-peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. The XOSC_Q2 line must be left unconnected. C51 and C71 can be omitted when using a reference signal.
6.2.5 Additional Filtering
In the 868/915 MHz reference design, C106 and L105 together with C105 build an optional filter to reduce emission at 699 MHz. This filter may be necessary for applications seeking compliance with ETSI EN 300-220, for more information, see DN017[6]. If this filtering is not necessary, C105 will work as a DC block (only necessary if there is a DC path in the antenna). C106 and L105 should in that case be left unmounted.
Additional external components (for example, an RF SAW filter) may be used in order to improve the performance in specific applications. The use of wire-wound inductors in the application circuit will also improve the RF performance and give higher output power. For more information, see DN017[6].
6.2.6 Power Supply Decoupling
The power supply must be properly decoupled close to the supply pins.
NOTE
Decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance.
The CC1150EM reference design should be followed closely (see [1] and [2]).
6.3 PCB Layout Recommendations
The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias.
The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias for good thermal performance and sufficiently low inductance to ground.
In the CC1150EM reference designs (see [1] and [2]), 5 vias are placed inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder-reflow process.
The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste coverage below 100%. See Figure 6-4 for top solder resist and top paste masks.
All the decoupling capacitors should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC1150 supply pin. Supply power filtering is very important.
Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. Routing in the ground plane underneath and between the chip, the balun/RF matching circuit and the decoupling capacitor’s ground vias should also be avoided. This improves the grounding and ensures the shortest possible return path for stray currents.
The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Please note that components smaller than those specified may have differing characteristics.
Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry.
It is strongly advised that the CC1150EM reference design (see [1] and [2]) layout is followed very closely in order to get the best performance. Gerber files and schematics for the reference designs are available for download from the TI website.
6.3.1 Package Description (QLP 16)
Figure 6-5 Recommended PCB Layout for Package (QLP 16)
Figure 6-5 is an illustration only and not to scale. There are five 10-mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC1150EM reference design ([1] and [2]).