ZHCSJU4I November 2006 – September 2018 CC1020
PRODUCTION DATA.
The configuration of the CC1020 device is done by programming the 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF Studio software. Complete descriptions of the registers are given in Section 5.22.1. After a RESET is programmed, all the registers have default values. The TEST registers also get default values after a RESET, and should not be altered by the user.
TI recommends using the register settings found using the SmartRF Studio software. These are the register settings that TI specifies across temperature, voltage, and process. Check the TI web site for regularly updates to the SmartRF Studio software.
| ADDRESS | ACRONYM | REGISTER NAME |
|---|---|---|
| 00h | MAIN | Main control register |
| 01h | INTERFACE | Interface control register |
| 02h | RESET | Digital module reset register |
| 03h | SEQUENCING | Automatic power-up sequencing control register |
| 04h | FREQ_2A | Frequency register 2A |
| 05h | FREQ_1A | Frequency register 1A |
| 06h | FREQ_0A | Frequency register 0A |
| 07h | CLOCK_A | Clock generation register A |
| 08h | FREQ_2B | Frequency register 2B |
| 09h | FREQ_1B | Frequency register 1B |
| 0Ah | FREQ_0B | Frequency register 0B |
| 0Bh | CLOCK_B | Clock generation register B |
| 0Ch | VCO | VCO current control register |
| 0Dh | MODEM | Modem control register |
| 0Eh | DEVIATION | TX frequency deviation register |
| 0Fh | AFC_CONTROL | RX AFC control register |
| 10h | FILTER | Channel filter / RSSI control register |
| 11h | VGA1 | VGA control register 1 |
| 12h | VGA2 | VGA control register 2 |
| 13h | VGA3 | VGA control register 3 |
| 14h | VGA4 | VGA control register 4 |
| 15h | LOCK | Lock control register |
| 16h | FRONTEND | Front end bias current control register |
| 17h | ANALOG | Analog modules control register |
| 18h | BUFF_SWING | LO buffer and prescaler swing control register |
| 19h | BUFF_CURRENT | LO buffer and prescaler bias current control register |
| 1Ah | PLL_BW | PLL loop bandwidth / charge pump current control register |
| 1Bh | CALIBRATE | PLL calibration control register |
| 1Ch | PA_POWER | Power amplifier output power register |
| 1Dh | MATCH | Match capacitor array control register, for RX and TX impedance matching |
| 1Eh | PHASE_COMP | Phase error compensation control register for LO I/Q |
| 1Fh | GAIN_COMP | Gain error compensation control register for mixer I/Q |
| 20h | POWERDOWN | Power-down control register |
| 21h | TEST1 | Test register for overriding PLL calibration |
| 22h | TEST2 | Test register for overriding PLL calibration |
| 23h | TEST3 | Test register for overriding PLL calibration |
| 24h | TEST4 | Test register for charge pump and IF chain testing |
| 25h | TEST5 | Test register for ADC testing |
| 26h | TEST6 | Test register for VGA testing |
| 27h | TEST7 | Test register for VGA testing |
| 40h | STATUS | Status information register (PLL lock, RSSI, calibration ready, and so on) |
| 41h | RESET_DONE | Status register for digital module reset |
| 42h | RSSI | Received signal strength register |
| 43h | AFC | Average received frequency deviation from IF (can be used for AFC) |
| 44h | GAUSS_FILTER | Digital FM demodulator register |
| 45h | STATUS1 | Status of PLL calibration results and so on (test only) |
| 46h | STATUS2 | Status of PLL calibration results and so on (test only) |
| 47h | STATUS3 | Status of PLL calibration results and so on (test only) |
| 48h | STATUS4 | Status of ADC signals (test only) |
| 49h | STATUS5 | Status of channel filter “I” signal (test only) |
| 4Ah | STATUS6 | Status of channel filter “Q” signal (test only) |
| 4Bh | STATUS7 | Status of AGC (test only) |