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ZHCSCR2 July 2014

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DBT|30
- MPDS019J

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcscr2_oa

8 Specifications

8.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC relative to V_SS	Supply voltage range	–0.3	2.75	V
V_(IOD)relative to V_SS	Open-drain I/O pins	–0.3	6	V
V_Irelative to V_SS	Input voltage range to all other pins	–0.3	VCC + 0.3	V
T_A	Operating free-air temperature range	–40	85	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

8.2 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range	–65	150	°C
V_ESD⁽¹⁾	Human Body Model (HBM) ESD stress voltage⁽²⁾	–2	2	kV
V_ESD⁽¹⁾	Charged Device Model (CDM) ESD stress voltage⁽³⁾	–500	500	V

(1) Electrostatic discharge (ESD) that measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM enables safe manufacturing with a standard ESD control process. Pins listed as 1000 V may actually have a higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM enables safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have a higher performance.

8.3 Recommended Operating Conditions

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_CC	Supply voltage		2.4	2.5	2.6	V
V_O	Output voltage range	SAFE			V_CC
		SMBC, SMBD, VEN			5.5	V
		ADREN, GPIO A, GPIO B, SDATA, SCLK, PWRM, LED1...5 (when used as GPO)			V_CC
V_IN	Input voltage range	BAT, VAUX, SMBA			1	V
		SMBD, SMBC, ALERT, DISP, PRES, KEYIN			5.5
		SDATA, GPIO A, GPIO B, LED1...5 (when used as GPI)			V_CC
T_OPR	Operating Temperature		–40		85	°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq78350		UNIT
		TSSOP (DBT)	QFN (RSM)
		30 PINS	32 PINS
R_{JA, High K}	Junction-to-ambient thermal resistance⁽²⁾	81.4	37.4	°C/W
R_JC(top)	Junction-to-case(top) thermal resistance⁽³⁾	16.2	30.6
R_JB	Junction-to-board thermal resistance⁽⁴⁾	34.1	7.7
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	0.4	0.4
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	33.6	7.5
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance⁽⁷⁾	n/a	2.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

8.5 Electrical Characteristics: Supply Current

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
I_CC	Operating mode current	No flash programming	650⁽¹⁾		μA
I_(SLEEP)	Low-power storage mode current	SLEEP mode	300⁽²⁾		μA
I_(SHUTDOWN)	Low-power SHUTDOWN mode current	SHUTDOWN mode	0.1	1	μA

(1) The actual current consumption of this mode fluctuates during operation over a 1-s period. The value shown is an average using the default data flash configuration.

(2) The actual current consumption of this mode fluctuates during operation over a user-configurable period. The value shown is an average using the default data flash configuration.

8.6 Electrical Characteristics: I/O

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OL	Output voltage low SMBC, SMBD, SDATA, SCLK, SAFE, ADREN, VEN, GPIO A, GPIO B, PWRM	I_OL = 0.5 mA			0.4	V
V_OL	Output voltage low LED1, LED2, LED3, LED4, LED5	I_OL = 3 mA			0.4
V_OH	Output voltage high SMBC, SMBD, SDATA, SCLK, SAFE, ADREN, VEN, GPIO A, GPIO B, PWRM	I_OH = –1 mA	V_CC – 0.5			V
V_IL	Input voltage low SMBC, SMBD, SDATA, SCLK, ALERT, DISP, SMBA, GPIO A, GPIO B, PRES, KEYIN		–0.3		0.8	V
V_IH	Input voltage high SMBC, SMBD, SDATA, SCLK, ALERT, SMBA, GPIO A, GPIO B		2		6	V
V_IH	Input voltage high DISP, PRES, KEYIN		2		V_CC + 0.3	V
C_IN	Input capacitance			5		pF
I_LKG	Input leakage current				1	µA

8.7 Electrical Characteristics: ADC

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	MAX	UNIT
Input voltage range	BAT, VAUX	–0.2	1	V
Conversion time		31.5		ms
Resolution (no missing codes)		16		bits
Effective resolution		14	15	bits
Integral nonlinearity		±0.03%		FSR⁽¹⁾
Offset error⁽²⁾		140	250	µV
Offset error drift⁽²⁾	T_A = 25°C to 85°C	2.5	18	V/°C
Full-scale error⁽³⁾		±0.1%	±0.7%
Full-scale error drift		50		PPM/°C
Effective input resistance⁽⁴⁾		8		MΩ

(1) Full-scale reference

(2) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference

(3) Uncalibrated performance. This gain error can be eliminated with external calibration.

(4) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average resistance.

8.8 Electrical Characteristics: Power-On Reset

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IT–	Negative-going voltage input		1.7	1.8	1.9	V
V_HYS	Power-on reset hysteresis		50	125	200	mV

8.9 Electrical Characteristics: Oscillator

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_(OSC)	Operating frequency				4.194	MHz
f_(EIO)	Frequency error⁽¹⁾⁽²⁾		–3%	0.25%	3%
f_(EIO)	Frequency error⁽¹⁾⁽²⁾	T_A = 20°C to 70°C	–2	0.25	2
t_(SXO)	Start-up time⁽³⁾			2.5	5	ms
LOW FREQUENCY OSCILLATOR
f_(LOSC)	Operating frequency			32.768		kHz
f_(LEIO)	Frequency error⁽²⁾⁽⁴⁾		–2.5%	0.25%	2.5%
f_(LEIO)	Frequency error⁽²⁾⁽⁴⁾	TA = 20°C to 70°C	–1.5	0.25	1.5
t_(LSXO)	Start-up time⁽⁵⁾				500	ms

(1) The frequency error is measured from 4.194 MHz.

(2) The frequency drift is included and measured from the trimmed frequency at V_CC = 2.5 V, TA = 25°C.

(3) The start-up time is defined as the time it takes for the oscillator output frequency to be within 1% of the specified frequency.

(4) The frequency error is measured from 32.768 kHz.

(5) The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.

8.10 Electrical Characteristics: Data Flash Memory

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_DR	Data retention	See note⁽¹⁾	10			Years
t_DR	Flash programming write-cycles	See note⁽¹⁾	20,000			Cycles
t_(WORDPROG)	Word programming time	See note⁽¹⁾			2	ms
I_(DDdPROG)	Flash-write supply current	See note⁽¹⁾		5	10	mA

(1) Specified by design. Not production tested.

8.11 Electrical Characteristics: Register Backup

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_(RB)	RB data-retention input current	V_(RB) > V_(RBMIN), VCC < VIT–			1500	nA
I_(RB)	RB data-retention input current	V_(RB) > V_(RBMIN), VCC < VIT–, TA = 0°C to 50°C		40	160
V_(RB)	RB data-retention voltage (1)		1.7			V

8.12 SMBus Timing Specifications

V_CC = 2.4 V to 2.6 V, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_SMB	SMBus operating frequency	SLAVE mode, SMBC 50% duty cycle	10		100	kHz
f_MAS	SMBus master clock frequency	MASTER mode, no clock low slave extend		51.2
t_BUF	Bus free time between start and stop		4.7			ms
t_HD:STA	Hold time after (repeated) start		4
t_SU:STA	Repeated start setup time		4.7
t_SU:STO	Stop setup time		4
t_HD:DAT	Data hold time	RECEIVE mode	0			ns
t_HD:DAT	Data hold time	TRANSMIT mode	300
t_SU:DAT	Data setup time		250
t_TIMEOUT	Error signal/detect	See note⁽¹⁾	25		35	ms
t_LOW	Clock low period		4.7			µs
t_HIGH	Clock high period	See note⁽²⁾	4		50
t_LOW:SEXT	Cumulative clock low slave extend time	See note⁽³⁾			25	ms
t_LOW:MEXT	Cumulative clock low master extend time	See note⁽⁴⁾			10
t_F	Clock/data fall time	(V_ILMAX – 0.15 V) to (V_IHMIN + 0.15 V)			300	ns
t_R	Clock/data rise time	0.9 VCC to (V_ILMAX – 0.15 V)			1000

(1) The bq78350 times out when any clock low exceeds t_TIMEOUT.

(2) t_HIGH:MAX is minimum bus idle time. SMBC = 1 for t > 50 μs causes a reset of any transaction in progress involving the bq78350.

(3) t_LOW:SEXTis the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to stop.

(4) t_LOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to stop.

Figure 1. SMBus Timing Diagram

8.13 Typical Characteristics

Figure 2. Internal Voltage Reference

Figure 4. LED Sink Current

Figure 6. HFO Frequency

Figure 3. ADC Offset Error

Figure 5. LFO Frequency