ZHCSDI4D March 2015 – October 2022 BQ25890 , BQ25892
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Functional Block Diagram
- 9.2
Feature Description
- 9.2.1 Device Power-On-Reset (POR)
- 9.2.2 Device Power Up from Battery without Input Source
- 9.2.3 Device Power Up from Input Source
- 9.2.4 Input Current Optimizer (ICO)
- 9.2.5 Boost Mode Operation from Battery
- 9.2.6 Power Path Management
- 9.2.7 Battery Charging Management
- 9.2.8 Battery Monitor
- 9.2.9 Status Outputs ( PG, STAT, and INT)
- 9.2.10 BATET (Q4) Control
- 9.2.11 Current Pulse Control Protocol
- 9.2.12 Input Current Limit on ILIM
- 9.2.13 Thermal Regulation and Thermal Shutdown
- 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
- 9.2.15 Battery Protection
- 9.2.16 Serial Interface
- 9.3 Device Functional Modes
- 9.4 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
9.2.3.3.1 D+/D– Detection Sets Input Current Limit (BQ25890)
The BQ25890 contains a D+/D– based input source detection to set the input current limit automatically. The D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter detections. When input source is plugged-in, the device starts standard USB BC1.2 detections. The USB BC1.2 is capable to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard adapter detection is applied to set the input current limit.
When DCP is detected, the device initates adjustable high voltage adapter handshake including MaxCharge?, etc. The handshake connects combinations of voltage source(s) and/or current sink on D+/D- to signal input source to raise output voltage from 5 V to 9 V / 12 V. The adjustable high voltage adapter handshake can be disabled by clearing MAXC_EN and/or HVDCP_EN bits.
Figure 9-1 USB D+/D- Detection| NON-STANDARD ADAPTER | D+ THRESHOLD | D- THRESHOLD | INPUT CURRENT LIMIT |
|---|---|---|---|
| Divider 1 | VD+ within V2P7_VTH | VD- within V2P0_VTH | 2.1A |
| Divider 2 | VD+ within V1P2_VTH | VD- within V1P2_VTH | 2A |
| Divider 3 | VD+ within V2P0_VTH | VD- within V2P7_VTH | 1A |
| Divider 4 | VD+ within V2P7_VTH | VD- within V2P7_VTH | 2.4A |
| ADJUSTABLE HIGH VOLTAGE HANDSHAKE | D+ | D- | OUTPUT |
|---|---|---|---|
| MaxCharge (12V) | I1P6MA_ISINK | V3p45_VSRC | 12 V |
| MaxCharge (9V) | V3p45_VSRC | I1P6MA_ISINK | 9 V |
After the Section 9.2.3.3 is done, an INT pulse is asserted to the host. In addition, the following registers including Input Current Limit register (IINLIM), VBUS_STAT, and SDP_STAT are updated as below:
| D+/D- DETECTION | INPUT CURRENT LIMIT (IINLIM)(1) | SDP_STAT | VBUS_STAT |
|---|---|---|---|
| USB SDP (USB500) | 500 mA | 1 | 001 |
| USB CDP | 1.5 A | 1 | 010 |
| USB DCP | 3.25 A | 1 | 011 |
| Divider 3 | 1 A | 1 | 110 |
| Divider 1 | 2.1 A | 1 | 110 |
| Divider 4 | 2.4 A | 1 | 110 |
| Divider 2 | 2 A | 1 | 110 |
| MaxCharge | 1.5 A | 1 | 100 |
| Unknown Adapter | 500 mA | 1 | 101 |