SLUSFH4A March 2025 – July 2025 BQ25858-Q1 , BQ25858B-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The device can be configured as buck-only using the MODE pin as described in MODE Pin Configuration section. In this mode, the Q3 and Q4 FETs can be removed from the system. An optional gate drive voltage can be provided using the DRV_SUP pin to reduce switching losses. Figure 8-25 shows a typical schematic when using the device as a buck with 48V input, configurable output voltage for USB-PD EPR and 5A output current.
| COMPONENT | VALUE | RECOMMENDED PART NO. |
|---|---|---|
| Q1, Q2 | 80 V, 2.8 mΩ | SIR680LDP-T1-RE3 |
| L1 | 10μH, 13mΩ | SRP1770TA-100M |