ZHCSGO5B June 2017 – March 2022 BQ25600 , BQ25600D
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Power-On-Reset (POR)
- 8.3.2 Device Power Up from Battery without Input Source
- 8.3.3 Power Up from Input Source
- 8.3.4 Boost Mode Operation From Battery
- 8.3.5 Host Mode and Standalone Power Management
- 8.3.6 Power Path Management
- 8.3.7 Battery Charging Management
- 8.3.8 Protections
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage.
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.
When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the system is always regulated at typically 50 mV above battery voltage. The status register VSYS_STAT bit goes high when the system is in minimum system voltage regulation.
Figure 8-7 System
Voltage vs Battery Voltage