The
PG pin is an open-drain output that by default indicates when a valid IN supply is present. It may also be configured to be a general purpose output (GPO) controlled through I2C or to be a level shifted version of the
MR input signal. Connect
PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication. Below is the description for each configuration:
- In its default state,
PG pulls to GND when the following conditions are met: VIN > VUVLO, VIN > VBAT+VSLP and VIN < VIN_OVP.
PG is high impedance when the input power is not within specified limits.
- MR shifted (MRS) output when the PG_MODE bits are set to 01.
PG is high impedance when the
MR input is high, and
PG pulls to GND when the
MR input is low.
- General purpose open drain output when setting the PG_MODE bits to 1x. The state of the
PG pin is then controlled through the GPO_PG bit, where if GPO_PG is 0 , the
PG pin is pulled to GND and if it is 1, the
PG pin is in high impedance.