ZHCSJD3C july 2018 – april 2023 BQ25150
PRODUCTION DATA
Low Power mode is a low quiescent current state while operating from the battery. The device will operate in low power mode when the LP pin is set low, VIN < VUVLO, MR pin is high and all I2C transactions and interrupts that started while in the Active Battery or Charging Modes have been completed and sent. During LP mode the VDD output is powered by BAT, the MR inputs are active and the I2C and ADC are disabled. All other circuits, such as oscillators, are in a low power or off state. The LS/LDO outputs will remain in the state set by the EN_LS_LDO bit prior to entering Low Power Mode. The device exits LP Mode when the LP pin is set high or VIN > VUVLO.
In the case that a faulty adapter with VIN > VOVP is connected to the device while LP pin is low, the device will be powered from the battery, but will operate in Active battery mode instead of Low Power mode regardless of the LP pin state.
When MR is held low while LP is low, the device will enter Active Battery Mode, this allows for the internal clocks of the device to be running and allow the MR long button press HW reset. I2C operation is also be possible during this condition. Note that as soon as the MR input is released and goes high, the device will go back to LP Mode tuning off all clocks. Note that if a HW reset has occurred while LP is low, MR must remain low until the power cycle has completed (PMID and LDO enable) to allow completion of the power up sequence.