SLUSA49C April 2010 – June 2015
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Battery Voltage Regulation
- 8.3.2 Battery Current Regulation
- 8.3.3 Input Adapter Current Regulation
- 8.3.4 Precharge
- 8.3.5 Charge Termination, Recharge, and Safety Timer
- 8.3.6 Power Up
- 8.3.7 Enable and Disable Charging
- 8.3.8 System Power Selector
- 8.3.9 Automatic Internal Soft-Start Charger Current
- 8.3.10 Converter Operation
- 8.3.11 Synchronous and Nonsynchronous Operation
- 8.3.12 Cycle-by-Cycle Charge Undercurrent Protection
- 8.3.13 Input Overvoltage Protection (ACOV)
- 8.3.14 Input Undervoltage Lockout (UVLO)
- 8.3.15 Battery Overvoltage Protection
- 8.3.16 Cycle-by-Cycle Charge Overcurrent Protection
- 8.3.17 Thermal Shutdown Protection
- 8.3.18 Temperature Qualification and JEITA Guideline
- 8.3.19 Timer Fault Recovery
- 8.3.20 PG Output
- 8.3.21 CE (Charge Enable)
- 8.3.22 Charge Status Outputs
- 8.3.23 Battery Detection
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
- RGE|24
散熱焊盤機械數據 (封裝 | 引腳)
- RGE|24
訂購信息
6 Pin Configuration and Functions
RGE Package
24-Pin VQFN
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ACDRV | 3 | O | AC adapter-to-system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET and the reverse-conduction-blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to source of the ACFET is used to slow down the ON and OFF times. |
| ACN | 1 | I | Adapter current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to GND for common-mode filtering. |
| ACP | 2 | I | Adapter current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to GND for common-mode filtering. |
| ACSET | 16 | I | Adapter current-set input. The voltage on the ACSET pin programs the input current-regulation set-point during dynamic power management (DPM) |
| BATDRV | 23 | O | Battery-to-system MOSFET driver output. Gate drive for the battery-to-system load BAT PMOS power FET to isolate the system from the battery to prevent current flow from the system to the battery, while allowing a low-impedance path from battery to system. Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the system load-voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical to allow a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times. |
| BTST | 22 | I | PWM high-side driver positive supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky diode from REGN to BTST. |
| CE | 4 | I | Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1-MΩ pulldown resistor. |
| GND | 17 | Low-current sensitive analog/digital ground. On PCB layout, connect with thermal underneath the IC. | |
| HIDRV | 21 | O | PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace. |
| ISET1 | 11 | I | Fast-charge current-set input. The voltage on the ISET1 pin programs the fast-charge current regulation set-point. To avoid early termination during the VT1 and VT2 range, fast-charge current must be higher than 2 times the termination current. |
| ISET2 | 15 | I | Precharge and termination current-set input. The voltage of ISET2 pin programs the precharge current regulation set-point and termination current trigger point. |
| LODRV | 19 | O | PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace. |
| PG | 8 | O | Open-drain power good status output. Active-LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active-HIGH when IC has an invalid VCC. PG can be used to drive an LED or communicate with a host processor. |
| PH | 20 | I | PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor). |
| REGN | 18 | O | PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the GND pin, close to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST. |
| SRN | 13 | I/O | Charge current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for common-mode filtering. |
| SRP | 14 | I/O | Charge current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to GND for common-mode filtering. |
| STAT1 | 5 | O | Open-drain charge-status pin to indicate various charger operations (see Table 2). |
| STAT2 | 9 | O | Open-drain charge-status pin to indicate various charger operations (see Table 2). |
| TS | 6 | I | Temperature qualification voltage input for battery pack negative-temperature-coefficient thermistor. Program the hot and cold temperature window with a resistor-divider from VREF to TS to GND. (see Figure 14). |
| TTC | 7 | I | Fast-charge safety timer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the fast-charge timer and termination are disabled. When this input is HIGH, the fast-charge timer is disabled, but termination is allowed. |
| VCC | 24 | I | IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from VCC to GND pin close to the IC. |
| VFB | 12 | I | Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage. |
| VREF | 10 | O | 3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming of voltage and current regulation and for programming the TS threshold. |
| Thermal Pad | — | — | Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal pad plane star-connecting to GND and to the ground plane for a high-current power converter. It also serves as a thermal pad to dissipate the heat. |