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ZHCSAF6H October 2012 – August 2015

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- MPQF124G
YFF|30
- MXBG359A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- QFND136Y

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Pin Voltage Range (with respect to GND)	IN	–0.3	22	V
	SW	–0.7	12	V
	BOOT	–0.3	20	V
	LDO,STAT, INT, /CHG, /PG, EN1, EN2, EN3, /CE, D+, D-, ILIM, ISET, VDPM, TS, SCL, SDA	–0.3	7	V
	SYS, BAT	–0.3	5	V
BOOT relative to SW		–0.3	7	V
Output Current (Continuous)	IN		2	A
Output Current (Continuous)	SYS, BAT		4	A
Output Sink Current	STAT, /CHG, /PG		5	mA
Operating free-air temperature range		–40	85	°C
Junction temperature, T_J		–40	125	°C
Input Power	IN		15	W
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages

		MIN	MAX	UNIT
V_IN	IN voltage range	4.35	18⁽¹⁾	V
V_IN	IN operating voltage range	4.35	10.5	V
I_IN	Input current		2	A
I_CHG	Current in charge mode, BAT		2	A
I_DISCHG	Current in discharge mode, BAT		4	A
R_ISET	Charge current programming resistor range	75		Ω
R_ILIM	Input current limit programming resistor range	105		Ω
P_IN	Input Power		12	W
T_J	Operating junction temperature range	0	125	°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. Small routing loops for the power nets in layout minimize switching noise.

8.4 Thermal Information

THERMAL METRIC^⁽¹⁾		YFF (30 PINS)	RGE (24 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	76.5	32.9	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	0.2	32.8	°C/W
R_θJB	Junction-to-board thermal resistance	44	10.6	°C/W
ψ_JT	Junction-to-top characterization parameter	1.6	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	43.4	10.7	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A	2.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_UVLO < V_IN < V_OVP and V_IN > V_BAT+V_SLP, T_J = 0ºC-125°C and T_J = 25°C for typical values (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT CURRENTS
I_IN	Supply current from IN		V_DPM < V_IN < V_OVP AND V_IN > V_BAT+V_SLP PWM switching, CE Enable		13		mA
			V_DPM < V_IN < V_OVP AND V_IN > V_BAT+V_SLP PWM switching, CE Disable			5	mA
			V_IN= 5.5V, 0°C< T_J < 85°C, High-Z Mode		170	225	μA
I_BAT	Battery discharge current in high impedance mode, (BAT, SW, SYS)		0°C< T_J < 85°C, VBAT = 4.2 V, VIN = 0V or 5V, High-Z Mode		16	22	μA
I_BAT	Battery discharge current in SYSOFF mode		0°C< T_J < 85°C, VBAT = 4.2 V, VIN < UVLO, SYSOFF Mode			1	μA
POWER-PATH MANAGEMENT
V_SYSREG	System Regulation Voltage		MINSYS stage (no DPM or DPPM)	–1%	3.52	1%	V
			MINSYS stage (DPM or DPPM active)	–1.50%	V_MINSYS –200mV	1.50%
			BATREG stage		V_BAT + I_CHG R_on
			SYSREG stage	V_BATREG +2.1%	V_BATREG +3.1%	V_BATREG +4.1%
V_SPLM	Enter supplement mode voltage threshold		V_BAT = 3.6V		V_BAT – 40mV		V
I_SPLM	Exit supplement mode current threshold		V_BAT = 3.6V		20		mA
t_DGL(SC1)	Deglitch Time, OUT Short Circuit during Discharge or Supplement Mode		Measured from (V_BAT – V_SYS) = 300 mV		740		μs
t_REC(SC1)	Recovery Time, OUT Short Circuit during Discharge or Supplement Mode				64		ms
BATTERY CHARGER
R_ON(BAT-SYS)	Internal battery charger MOSFET on-resistance		Measured from BAT to SYS, V_BAT = 4.2V (WCSP)		20	30	mΩ
R_ON(BAT-SYS)	Internal battery charger MOSFET on-resistance		Measured from BAT to SYS, V_BAT = 4.2V (QFN)		30	40	mΩ
V_BATREG	I²C host mode		Operating in voltage regulation, Programmable Range	3.5		4.44	V
	SA mode or I²C default mode				4.2
	Voltage Regulation Accuracy		T_J = 25°C	–0.5%		0.5%
	Voltage Regulation Accuracy		T_J = 0°C to 125°C	–0.75%		0.75%
I_CHG	Fast Charge Current Range		V_LOWV ≤ V_BAT < V_BAT(REG)	500		2000	mA
	Fast Charge Current Accuracy		I²C mode	–7%		7%
I_CHG-LOW	Low Charge Current Setting		Set via I²C	297	330	363	mA
K_ISET	Programmable Fast Charge Current Factor			232.5	250	267.5	AΩ
V_ISET	Maximum ISET pin voltage (in regulation)				0.42		V
R_ISET-SHORT	Short circuit resistance threshold			45	55	75	Ω
V_LOWV	Pre-charge to fast charge threshold		Rising	2.9	3	3.1	V
V_LOWV	Hysteresis for V_LOWV		Battery voltage falling		100		mV
I_PRECHG	Pr-charge current (V_BATUVLO < V_BAT < V_LOWV)		Ipre-chg is a precentile of the external fast charge settings.	8	10	12	%
t_DGL(LOWV)	Deglitch time for pre-charge to fast charge transition				32		ms
V_{BAT_UVLO}	Battery Under voltage lockout threshold		V_BAT rising	2.37	2.5	2.63	V
	Battery UVLO hysteresis				200		mV
V_BATSHRT	Trickle charge to pre-charge threshold			1.9	2	2.1	V
	Hysteresis for VBATSHRT		Battery voltage falling		100		mV
I_BATSHRT	Trickle charge mode charge current (V_BAT < V_BATSHRT)			25	35	50	mA
t_DGL(BATSHRT)	Deglitch time for trickle charge to pre-charge transition				256		us
I_TERM	Termination Current Threshold		Termination current on SA only		10		%ICHG
I_TERM	Termination Current Threshold Tolerance			–10%		10%
t_DGL(TERM)	Deglitch time for charge termination		Both rising and falling, 2-mV over-drive, t_RISE, t_FALL = 100 ns		64		ms
V_RCH	Recharge threshold voltage		Below V_BATREG	70	115	160	mV
t_DGL(RCH)	Deglitch time		V_BAT falling below V_RCH, t_FALL = 100 ns		32		ms
BATTERY DETECTION
V_{BATREG_HI}	Battery Detection High Regulation Voltage		Same as V_BATREG		V_BATREG		V
V_{BATREG_LO}	Battery Detection Low Regulation Voltage		360 mV offset from V_BATREG		V_BATREG –480mV		V
V_{BATDET Hi}	Battery detection comparator		V_BATREG = VBATREG_HI		V_BATREG –120mV		V
V_{BATDET LO}	Battery detection comparator		V_BATREG = V_{BATREG_LO}		V_BATREG +120mV		V
I_DETECT	Battery Detection Current Sink		Always on during battery detection		7.5		mA
t_DETECT	Battery detection time		For both V_{BATREG_HI} and V_{BATREG_LO}		32		ms
Tsafe	Safety Timer Accuracy			–10%		+10%
INPUT PROTECTION
I_IN	Input current limiting		I_{IN_LIMIT} = 100 mA	90	95	100	mA
			I_{IN_LIMIT} = 150 mA	135	142.5	150
			I_{IN_LIMIT} = 500 mA	450	475	500
			I_{IN_LIMIT} = 900 mA	810	860	910
			I_{IN_LIMIT} = 1500 mA	1400	1475	1550
			I_{IN_LIMIT} = 2000 mA	1850	1950	2050
			I_{IN_LIMIT} = External
I_LIM	Maximum input current limit programmable range for IN input			500		2000	mA
K_ILIM	Maximum input current factor for IN input		I_LIM = 500 mA to 2.0 A	240	270	300	AΩ
V_ILIM	Maximum ILIM pin voltage (in regulation)				0.42		V
I_IN /I_ILIM	Ratio between input current and the ILIM pin current in external control or stand alone mode		External ILIM control or stand alone		540		A/A
R_ILIM-SHORT	Short circuit resistance threshold				55	75	Ω
V_{IN_DPM}	V_{IN_DPM} threshold range		SA mode	4.2		10	V
	V_{IN_DPM} threshold range		I²C mode	4.2		4.76
	V_{IN_DPM} threshold for USB Input in SA mode		USB100, USB150, USB500, USB900, current limit selected. Also I²C register default.	4.27	4.36	4.45
	V_{IN_DPM} threshold with adaptor current limit and VDPM shorted to GND		Must set to external resistor settings via the EN1/EN2 pins or the I²C register interface.	V_{IN_DPM} . –2%	V_{IN_DPM}	V_{IN_DPM} . +2%
	V_{IN_DPM} threshold Accuracy		Both I²C and SA mode	–2%		2%
V_{REF_DPM}	DPM regulation voltage		External resistor setting only	1.15	1.2	1.25	V
V_{DPM_SHRT}	VIN_DPM short threshold		If VDPM is shorted to ground, V_{IN_DPM} threshold will use internal default value		0.3		V
V_UVLO	IC active threshold voltage		V_IN rising	3.15	3.35	3.5	V
V_UVLO	IC active hysteresis		V_IN falling from above V_UVLO		175		mV
V_SLP	Sleep-mode entry threshold, V_IN-VBAT		2.0 V ≤ V_BAT ≤ V_BATREG, V_IN falling	0	50	100	mV
V_SLP	Sleep-mode exit hysteresis, V_IN-VBAT		2.0 V ≤ V_BAT ≤ V_BATREG	40	100	160	mV
t_DGL(SLP)	Deglitch time for IN rising above VIN+VSLP_EXIT		Rising voltage, 2-mV over drive, t_RISE = 100 ns		32		ms
V_OVP	Input supply OVP threshold voltage		IN rising	Input OVP –200mV	Input OVP	Input OVP +200mV	V
V_OVP	VOVP hysteresis		IN falling from V_OVP		100		mV
t_DGL(OVP)	Deglitch time for IN Rising above VOVP		IN rising voltage, t_RISE = 100 ns		32		ms
V_BOVP	Battery OVP threshold voltage		V_BAT threshold over V_BATREG to turn off charger during charge	102.5	105	107.5	% V_BATREG
V_BOVP	VBOVP hysteresis		Lower limit for V_BAT falling from above V_BOVP		1		% V_BATREG
t_DGL(BOVP)	BOVP Deglitch		Battery entering/exiting BOVP		1		ms
PWM CONVERTER
R_ON(BLK)	Internal blocking MOSFET on-resistance		Measured from IN to PMID (WCSP & QFN)		60	100	mΩ
R_ON(HS)	Internal high-side MOSFET on-resistance		Measured from PMID to SW (WCSP & QFN)		100	150	mΩ
R_ON(LS)	Internal low-side MOSFET on-resistance		Measured from SW to PGND (WCSP & QFN)		110	165	mΩ
I_CbC	Cycle-by-cycle current limit		VSYS shorted	2.6	3.2	3.8	A
f_OSC	Oscillator frequency			2.7	3	3.3	MHz
D_MAX	Maximum duty cycle				95%
D_MIN	Minimum duty cycle			0%
T_SHTDWN	Thermal trip				150		°C
T_SHTDWN	Thermal hysteresis				10
T_REG	Thermal regulation threshold		Charge current begins to cut off		125
LDO (LINEAR DROPOUT)
V_LDO	LDO Output Voltage	bq24251 and bq24253	V_IN = 5.5 V, I_LDO = 0 to 50 mA	4.65	4.95	5.25	V
I_LDO	Maximum LDO Output Current			50			mA
V_DO	LDO Dropout Voltage (V_IN – V_LDO)		V_IN = 5.0 V, I_LDO = 50 mA		200	300	mV
BATTERY-PACK NTC MONITOR (1)
V_HOT	High temperature threshold		V_TS falling	29.6	30	30.4	% V_LDO
V_HYS(HOT)	Hysteresis on high threshold		V_TS rising		1
V_WARM	Warm temperature threshold		V_TS falling	37.9	38.3	38.7
V_HYS(WARM)	Hysteresis on warm temperature threshold		V_TS rising		1
V_COOL	Cool temperature threshold		V_TS rising	56.1	56.5	56.9
V_HSY(COOL)	Hysteresis on cool temperature threshold		V_TS falling		1
V_COLD	Low temperature threshold		V_TS rising	59.6	60	60.4
V_HYS(COLD)	Hysteresis on low threshold		V_TSfalling		1
V_FRZ	Freeze temperature threshold		V_TS rising	62	62.5	63
V_HYS(FRZ)	Hysteresis on freeze threshold		V_TS falling		1
V_{TS_DIS}	TS disable threshold			70		73
t_DGL(TS)	Deglitch time on TS change				32		ms
INPUTS (EN1, EN2, EN2, CE, CE1, CE2, BATREG, SCL, SDA, DBP)
V_IH	Input high threshold			1			V
V_IL	Input low threshold					0.4	V
STATUS OUTPUTS (CHG, PG, STAT, INT, BATRDY)
V_OL	Low-level output saturation voltage		I_O = 5 mA, sink current			0.4	V
I_IH	High-level leakage current		Hi-Z and 5V applies			1	µA
TIMERS
t_SAFETY	45 min safety timer				2700		s
	6 hr safety timer				21600
	9 hr safety timer				32400
t_WATCH-DOG	Watch dog timer				50		s
D+/D– DETECTION
I_{DP_SRC}	D+ current source for DCD		DCD	7		13	µA
R_{DM_DWN}	D– pull-down resistance for DCD		DCD	14.25		24.8	kΩ
V_{DP_LOW}	D+ low comparator threshold for DCD		DCD	0.85	0.9	0.95	V
V_{DP_SRC}	D+ source voltage for Primary Detection		Primary Detection	0.5	0.6	0.7	V
I_{DP_SRC_PD}	D+ source voltage output current for Primary Detection		Primary Detection	200			µA
I_{DM_SINK}	D– sink current for Primary Detection		Primary Detection	50	100	150	µA
V_{DAT_REF}	Primary Detection threshold		Primary Detection	250	325	400	mV
V_LGC	Primary Detection threshold		Primary Detection	0.85	0.9	0.95	V
V_{DM_SRC}	D- source voltage for Secondary Detection		Secondary Detection	0.5	0.6	0.7	V
I_{DM_SRC_PD}	D- source voltage output current for Secondary Detection		Secondary Detection	200			µA
I_{DP_SINK}	D+ sink current for Secondary Detection		Secondary Detection	50	100	150	µA
V_{DAT_REF}	Secondary Detection threshold		Secondary Detection	250	325	400	mV
V_{ATT_LO}	Apple/TomTom detection low threshold		Apple/TomTom Detection	1.8	1.85	1.975	V
V_{ATT_HI}	Apple/TomTom detection high threshold		Apple/TomTom Detection	3.2	3.5	3.8	V
C_I	Input Capacitance		D– , switch open		4.5		pF
C_I	Input Capacitance		D+, switch open		4.5		pF
I_{D_LKG}	Leakage Current into D+/D–		D–, switch open	–1		1	µA
I_{D_LKG}	Leakage Current into D+/D–		D+, switch open	–1		1	µA

8.6 Typical Characteristics

bq24251 bq24253 bq2425x_batt_det_lusba1a.gif

V_BAT = 3.8 V	V_IN = 5 V	V_REG = 4.2 V
I_CHG = 0.5 A	I_LIM = 1 A

Figure 1. Battery Detection

I_CHG = 2 A	V_IN = 5 V	V_REG = 4.2 V

Figure 3. Efficiency vs Battery Voltage

V_REG = 4.2 V

Figure 5. Efficiency vs Output Current

V_IN = 0 V	SYSOFF = 0	Charge Enabled
	BAT & SYS are Shorted

Figure 7. BAT IQ, SYSOFF = 0

Charge EN and DIS

No Battery and System

Figure 9. Input IQ With Charge DIS and EN

V_BAT = 3.3 V	V_IN = 5 V	V_REG = 4.2 V
	I_LIM = 2 A

Figure 11. I_CHG Accuracy with Internal Settings, V_BAT = 3.3 V

Figure 13. Ratio Between VILIM and IIN With External ILIM Control

bq24251 bq24253 bq2425x_batt_removal_lusba1a.gif

V_BAT = 3.8 V	V_IN = 6 V	V_REG = 4.2 V
I_CHG = 1 A	I_LIM = 1 A

Figure 2. Battery Removal

V_IN = 5 V	No Battery	I_LIM = 2 A
V_REG = 4.2 V	Charge Disable

Figure 4. System Voltage Regulation vs Load Current

V_REG = 3.6 V

Figure 6. Efficiency vs Output Current

V_IN = 0 V	SYSOFF = 1	Charge Enabled
	BAT & SYS are Shorted

Figure 8. BAT IQ, SYSOFF = 1

Charge EN

Hi-Z EN

Figure 10. Input IQ with Charge Enable and Hi-Z

V_BAT = 3.8 V	V_IN = 5 V	V_REG = 4.2 V
	I_LIM = 2 A

Figure 12. I_CHG Accuracy with Internal Settings, V_BAT = 3.8 V

bq24251 bq24253 Input_OVP_Event2_SLUSBA1.gif

V_BAT = 3.9 V	V_OVP = 10.5 V
I_CHG = 1 A	I_LIM = 1 A

Figure 14. Input OVP Event with INT