ZHCSD66B January 2014 – May 2017
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Undervoltage Lockout
- 8.3.2 Power On
- 8.3.3 Power-Path Management
- 8.3.4
Battery Charging
- 8.3.4.1 Charge Current Translator
- 8.3.4.2 Battery Detection and Recharge
- 8.3.4.3 Termination Disable (TD Input, bq24230H)
- 8.3.4.4 Adjustable Termination Threshold (ITERM Input, bq24232H)
- 8.3.4.5 Dynamic Charge Timers (TMR Input)
- 8.3.4.6 Status Indicators (PGOOD, CHG)
- 8.3.4.7 Thermal Regulation and Thermal Shutdown
- 8.3.5 Battery Pack Temperature Monitoring
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
RGT Package
16 Pins
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NUMBER | |||
| '230H | '232H | |||
| BAT | 2,3 | 2, 3 | I/O | Charger Power Stage Output and Battery Voltage Sense Input. Connect BAT to the positive terminal of the battery. Bypass BAT to VSS with a 4.7-μF to 47-μF ceramic capacitor. |
| CE | 4 | 4 | I | Charge Enable Active-Low Input. Connect CE to a high logic level to place the battery charger in standby mode. In standby mode, OUT is active and battery supplement mode is still available. Connect CE to a low logic level to enable the battery charger. CE is internally pulled down with approximately 285 kΩ. Do not leave CE unconnected to ensure proper operation. |
| CHG | 9 | 9 | O | Open-Drain Charging Status Indication Output. CHG pulls to VSS when the battery is charging. CHG is high impedance when charging is complete and when charger is disabled. |
| EN1 | 6 | 6 | I | Input Current Limit Configuration Inputs. Use EN1 and EN2 control the maximum input current and enable USB compliance. See Table 1 for the description of the operation states. EN1 and EN2 are internally pulled down with approximately 285 kΩ. Do not leave EN1 or EN2 unconnected to ensure proper operation. |
| EN2 | 5 | 5 | I | |
| ILIM | 12 | 12 | I | Adjustable Current Limit Programming Input. Connect a 3.1-kΩ to 7.8-kΩ resistor from ILIM to VSS to program the maximum input current (EN2=1, EN1=0). The input current includes the system load and the battery charge current. |
| IN | 13 | 13 | I | Input Power Connection. Connect IN to the connected to external DC supply (AC adapter or USB port). The input operating range is 4.35 V to 6.6 V. The input can accept voltages up to 26 V without damage but operation is suspended. Connect bypass capacitor 1 μF to 10 μF to VSS. |
| ISET | 16 | 16 | I/O | Fast-Charge Current Programming Input. Connect a 3-kΩ to 36-kΩ resistor from ISET to VSS to program the fast-charge current level. Charging is disabled if ISET is left unconnected. While charging, the voltage at ISET reflects the actual charging current and can be used to monitor charge current. See the Charge Current Translator section for more details. |
| ITERM | - | 15 | I | Termination Current Programming Input. Connect a 0-Ω to 15-kΩ resistor from ITERM to VSS to program the termination current. Leave ITERM unconnected to set the termination current to the internal default 10% threshold. |
| OUT | 10,11 | 10, 11 | O | System Supply Output. OUT provides a regulated output when the input is below the OVP threshold and above the regulation voltage. When the input is out of the operation range, OUT is connected to VBAT. Connect OUT to the system load. Bypass OUT to VSS with a 4.7-μF to 47-μF ceramic capacitor. |
| PGOOD | 7 | 7 | O | Open-drain Power Good Status Indication Output. PGOOD pulls to VSS when a valid input source is detected. PGOOD is high-impedance when the input power is not within specified limits. Connect PGOOD to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication. |
| TD | 15 | - | I | Termination Dsable Input. Connect TD high to disable charger termination. Connect TD to VSS to enable charger termination. TD is checked during start-up only and cannot be changed during operation. See the TD section in this data sheet for a description of the behavior when termination is disabled. TD is internally pulled down to VSS with approximately 285 kΩ. Do not leave TD unconnected to ensure proper operation. |
| Thermal Pad | – | An internal electrical connection exists between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as the primary ground input for the device. The VSS pin must be connected to ground at all times. | ||
| TMR | 14 | 14 | I | Timer Programming Input. TMR controls the precharge and fast-charge safety timers. Connect TMR to VSS to disable all safety timers. Connect a 18-kΩ to 72-kΩ resistor between TMR and VSS to program the timers a desired length. Leave TMR unconnected to set the timers to the 5-hour fast charge and 30-minute precharge default timer values. |
| TS | 1 | 1 | I | External NTC Thermistor Input. Connect the TS input to the NTC thermistor in the battery pack. TS monitors a 10-kΩ NTC thermistor. For applications that do not use the TS function, connect a 10-kΩ fixed resistor from TS to VSS to maintain a valid voltage level on TS. |
| VSS | 8 | 8 | – | Ground. Connect to the thermal pad and to the ground rail of the circuit. |