ZHCSIF0N September 2008 – October 2021 BQ24072 , BQ24073 , BQ24074 , BQ24075 , BQ24079
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Undervoltage Lockout (UVLO)
- 9.3.2 Power On
- 9.3.3 Overvoltage Protection (OVP)
- 9.3.4 Dynamic Power Path Management
- 9.3.5
Battery Charging
- 9.3.5.1 Charge Current Translator
- 9.3.5.2 Adjustable Termination Threshold (ITERM Input, BQ24074)
- 9.3.5.3 Termination Disable (TD Input, BQ24072, BQ24073)
- 9.3.5.4 Battery Detection and Recharge
- 9.3.5.5 Battery Disconnect (SYSOFF Input, BQ24075, BQ24079)
- 9.3.5.6 Dynamic Charge Timers (TMR Input)
- 9.3.5.7 Status Indicators ( PGOOD, CHG)
- 9.3.5.8 Thermal Regulation and Thermal Shutdown
- 9.3.6 Battery Pack Temperature Monitoring
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1 Application Information
- 10.2 Typical Application
- 10.3 System Examples
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGT|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGT|16
訂購信息
9.3.2 Power On
When VIN exceeds the UVLO threshold, the BQ2407x powers up. While VIN is below VBAT + VIN(DT), the host commands at the control inputs ( CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and OUT pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT to OUT is ON. (If SYSOFF is high, Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.
Once VIN rises above VBAT + VIN(DT), PGOOD is driven low to indicate the valid power status and the CE, EN1, and EN2 inputs are read. The device enters standby mode if (EN1 = EN2 = HI) or if an input overvoltage condition occurs. In standby mode, Q1 is OFF and Q2 is ON so OUT is connected to the battery input. (If SYSOFF is high, FET Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.
When the input voltage at IN is within the valid range: VIN > UVLO AND VIN > VBAT + VIN(DT) AND VIN < VOVP, and the EN1 and EN2 pins indicate that the USB suspend mode is not enabled [(EN1, EN2) ≠ (HI, HI)] all internal timers and other circuit blocks are activated. The device then checks for short-circuits at the ISET and ILIM pins. If no short conditions exists, the device switches on the input FET Q1 with a 100mA current limit to checks for a short circuit at OUT. When VOUT is above VO(SC1), the FET Q1 switches to the current limit threshold set by EN1, EN2 and RILIM and the device enters into the normal operation. During normal operation, the system is powered by the input source (Q1 is regulating), and the device continuously monitors the status of CE, EN1 and EN2 as well as the input voltage conditions.
Figure 9-1 Startup Flow Diagram