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ZHCSK30B August 2019 – April 2020 AMC1336

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DWV|8
- MPDS382B

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

Table 9. Electrical Characteristics

minimum and maximum specifications apply from T_A = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at T_A = 25°C, AVDD = 5 V, DVDD = 3.3 V, and f_CLKIN = 20 MHz (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
R_IN	Single-ended input resistance	AINN = AGND	0.1	1.5		GΩ
R_IND	Differential input resistance		0.16	1.5		GΩ
C_IN	Single-ended input capacitance	AINN = AGND, f_CLKIN = 20 MHz		2		pF
C_IND	Differential input capacitance	f_CLKIN = 20 MHz		2		pF
I_IB	Input bias current	AINP = AINN = AGND; I_IB = (I_AINP + I_AINN) / 2	–10	±3	10	nA
TCI_IB	Input bias current drift	AINP = AINN = AGND; I_IB = (I_AINP + I_AINN) / 2		–14		pA/°C
I_IO	Input offset current	I_IO = I_AINP – I_AINN	–5	±1	5	nA
CMTI	Common-mode transient immunity	\|AGND – DGND\| = 1 kV	80	115		kV/µs
DC ACCURACY
	Resolution	Decimation filter output set to 16 bits	16			Bit
INL	Integral nonlinearity⁽²⁾	Resolution: 16 bits	–4	±1.6	4	LSB
E_O	Offset error	Initial, at T_A = 25°C, AINP = AINN = AGND	–0.5	±0.03	0.5	mV
TCE_O	Offset error drift⁽³⁾		–4	±0.6	4	µV/°C
E_G	Gain error⁽¹⁾	Initial, at T_A = 25°C, V_AINP = 1 V or V_AINN = –1 V, AINN = AGND	–0.25	±0.02	0.25	%
TCE_G	Gain error drift⁽⁴⁾		–40	±20	40	ppm/°C
CMRR	Common-mode rejection ratio	AINP = AINN, f_IN = 0 Hz, V_{CM min} ≤ V_CM ≤ V_{CM max}		–104		dB
CMRR	Common-mode rejection ratio	AINP = AINN, f_IN = 10 kHz, –0.5 V ≤ V_IN ≤ 0.5 V		–96		dB
PSRR	Power-supply rejection ratio	PSRR vs AVDD, at DC		–83		dB
PSRR	Power-supply rejection ratio	PSRR vs AVDD, 100-mV and 10-kHz ripple		–83		dB
AC ACCURACY
SNR	Signal-to-noise ratio	V_IN = 2 V_PP, f_IN = 1 kHz	82	87		dB
SINAD	Signal-to-noise + distortion	V_IN = 2 V_PP, f_IN = 1 kHz	79	85		dB
THD	Total harmonic distortion	V_IN = 2 V_PP, f_IN = 1 kHz		–91	–80	dB
SFDR	Spurious-free dynamic range	V_IN = 2 V_PP, f_IN = 1 kHz	80	92		dB
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
I_IN	Input current	DGND ≤ V_IN ≤ DVDD			7	µA
C_IN	Input capacitance			4		pF
V_IH	High-level input voltage		0.7 x DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 x DVDD	V
DIGITAL OUTPUT (CMOS)
C_LOAD	Output load capacitance	f_CLKIN = 21 MHz		15	30	pF
V_OH	High-level output voltage	I_OH = –20 µA	DVDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 µA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
POWER SUPPLY
AVDD_POR	AVDD power-on reset threshold voltage	AVDD falling	2.4	2.6	2.8	V
I_AVDD	High-side supply current	3 V ≤ AVDD ≤ 3.6 V		6.8	9	mA
I_AVDD	High-side supply current	4.5 V ≤ AVDD ≤ 5.5 V		7.8	10.5	mA
I_DVDD	Controller-side supply current	2.7 V ≤ DVDD ≤ 3.6 V, C_LOAD = 15 pF		3.4	5	mA
I_DVDD	Controller-side supply current	4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD = 15 pF		3.7	6	mA

(1) The typical value includes one sigma statistical variation.

(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(3) Offset error drift is calculated using the box method, as described by the following equation:
TCE_O = (value_MAX - value_MIN) / TempRange

(4) Gain error drift is calculated using the box method, as described by the following equation:
TCE_G (ppm) = ((value_MAX - value_MIN) / (value x TempRange)) X 10⁶