The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). As described by Equation 2, a very simple filter built with minimal effort and hardware, is a sinc³-type filter:

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-order modulator. All characterization in this document is also done with a sinc³ filter with an oversampling ratio (OSR) of 256 and an output word width of 16 bits, unless specified otherwise. The measured effective number of bits (ENOB) as a function of the OSR is illustrated in Figure 8-3 of the Section 8.2 section.

A Delta Sigma Modulator Filter Calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter order to achieve the desired output resolution and filter response time.

An example code for implementing a sinc³ filter in an FPGA is discussed in the Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for download at www.ti.com.

For modulator output bitstream filtering, a device from TI's C2000? or Sitara? microcontroller families is recommended. These families support up to eight channels of dedicated hardwired filter structures that significantly simplify system level design by offering two filtering paths per channel: one providing high-accuracy results for the control loop and one fast-response path for overcurrent detection.

A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter order to achieve the desired output resolution and filter response time.