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ZHCSPG8 February 2022 AMC1306M05-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DWV|8
- MPDS382B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcspg8_oa

6.8 Electrical Characteristics

minimum and maximum specifications are at T_A = –40°C to 125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP = –50 mV to 50 mV, INN = 0 V, and sinc³ filter with OSR = 256 (unless otherwise noted); typical specifications are at T_A = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_CMov	Commonmode overvoltage detection level	(INP + INN) / 2 to AGND	AVDD – 2			V
C_IN	Single-ended input capacitance	INN = AGND		4		pF
C_IND	Differential input capacitance			2		pF
R_IN	Single-ended input resistance	INN = AGND		4.75		kΩ
R_IND	Differential input resistance			4.9		kΩ
I_IB	Input bias current	INP = INN = AGND, I_IB = I_BP + I_BN	–97	–72	–57	μA
I_IO	Input offset current			±10		nA
CMTI	Common-mode transient immunity		100	150		kV/μs
CMRR	Common-mode rejection ratio	INP = INN, f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–99		dB
CMRR	Common-mode rejection ratio	INP = INN, f_IN from 0.1 Hz to 50 kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–98		dB
BW	Input bandwidth			800		kHz
DC ACCURACY
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
INL	Integral nonlinearity⁽²⁾	Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V	–4	±1	4	LSB
INL	Integral nonlinearity⁽²⁾	Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V	–5	±1.5	5	LSB
E_O	Offset error⁽¹⁾	T_A = 25°C, INP = INN = GND1	–50	±2.5	50	μV
TCE_O	Offset error temperatrure drift⁽³⁾		–1	±0.25	1	μV/°C
E_G	Gain error	T_A = 25°C	–0.2%	±0.005%	0.2%
TCE_G	Gain error temperature drift⁽⁴⁾		–40	±20	40	ppm/°C
PSRR	Power-supply rejection ratio	INP = INN = AGND, AVDD from 3.0 V to 5.5 V, at DC		–108		dB
PSRR	Power-supply rejection ratio	INP = INN = AGND, AVDD from 3.0 V to 5.5 V, 10 kHz / 100 mV ripple		–107		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1 kHz	78	82.5		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	77.5	82.3		dB
THD	Total harmonic distortion⁽⁵⁾	4.5 V ≤ AVDD ≤ 5.5 V, f_IN = 1 kHz, 5 MHz ≤ f_CLKIN ≤ 21 MHz		–98	–84	dB
THD	Total harmonic distortion⁽⁵⁾	3.0 V ≤ AVDD ≤ 3.6 V, f_IN = 1 kHz, 5 MHz ≤ f_CLKIN ≤ 20 MHz		–93	–83	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	83	100		dB
CMOS LOGIC WITH SCHMITT-TRIGGER
I_IN	Input current	DGND ≤ V_IN ≤ DVDD	0		7	μA
C_IN	Input capacitance			4		pF
V_IH	High-level input voltage		0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × DVDD	V
C_LOAD	Output load capacitance			30		pF
V_OH	High-level output voltage	I_OH = –4 mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
POWER SUPPLY
I_AVDD	High-side supply current	3.0 V ≤ AVDD ≤ 3.6 V		6.3	8.5	mA
I_AVDD	High-side supply current	4.5 V ≤ AVDD ≤ 5.5 V		7.2	9.8	mA
I_DVDD	Low-side supply current	2.7 V ≤ DVDD ≤ 3.6 V, C_LOAD = 15 pF		3.3	4.8	mA
I_DVDD	Low-side supply current	4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD = 15 pF		3.9	6.0	mA
AVDD_UV	High-side undervoltage detection threshold	AVDD rising	2.45	2.7	2.9	V
AVDD_UV	High-side undervoltage detection threshold	AVDD falling	2.4	2.6	2.8	V
DVDD_UV	Low-side undervoltage detection threshold	DVDD rising	2.2	2.45	2.65	V
DVDD_UV	Low-side undervoltage detection threshold	DVDD falling	1.75		2.2	V

(1) This parameter is input referred.

(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(3) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCE_O = (E_O,MAX – E_O,MIN) / TempRange where E_O,MAX and E_O,MIN refer to the maximum and minimum E_O values measured within the temperature range (–40 to 125℃).

(4) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCE_G (ppm) = ((E_G,MAX - E_G,MIN) / TempRange) x 10⁴ where E_G,MAX and E_G,MIN refer to the maximum and minimum E_G values (in %) measured within the temperature range (–40 to 125℃).

(5) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.