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SPRS657F February 2010 – January 2017 AM1705

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

PTP|176

散熱焊盤機械數據 (封裝 | 引腳)

PTP|176
- PPTD141B

訂購信息

8 Mechanical Packaging and Orderable Information

This section describes the device orderable part numbers, packaging options, materials, thermal and mechanical parameters.

8.1 Thermal Data for PTP

The following table(s) show the thermal resistance characteristics for the PowerPAD^TM PTP mechanical package.

Table 8-1 Thermal Resistance Characteristics (PowerPAD^TM Package) [PTP]"

No.			°C/W⁽¹⁾	°C/W⁽²⁾	°C/W⁽³⁾	°C/W⁽⁴⁾	AIR FLOW (m/s)⁽⁵⁾
1	RΘ_JC	Junction-to-case	7.8	9.4	8.6	10.1	N/A
2	RΘ_JB	Junction-to-board	6.2	9.9	7.1	10.6	N/A
3	RΘ_JA	Junction-to-free air	21.3	27.9	23.2	30.6	0.00
4	RΘ_JMA	Junction-to-moving air	14.3	20.2		22.6	0.50
5			13.1	18.6		21.0	1.00
6			12.1	17.4		19.6	2.00
7			11.2	16.2		18.2	4.00
8	Psi_JT	Junction-to-package top	0.5	0.7		0.8	0.00
9			0.6	0.9		1.0	0.50
10			0.7	1.0		1.1	1.00
11			0.8	1.1		1.3	2.00
12			1.0	1.3		1.5	4.00
13	Psi_JB	Junction-to-board	6.3	9.5		10.8	0.00
14			5.9	8.8		9.9	0.50
15			5.9	8.7		9.8	1.00
16			5.8	8.6		9.7	2.00
17			5.8	8.5		9.6	4.00

(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness. Power dissipation of 1W and ambient temp of 70C assumed.

(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper thickness 2oz (70um) top and bottom.

(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper thickness 1oz (35um) top and bottom.

(5) m/s = meters per second

8.2 Supplementary Information About the 176-pin PTP PowerPAD™ Package

This section highlights a few important details about the 176-pin PTP PowerPAD™ package. Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (SLMA002) should be consulted when creating a PCB footprint for this device.

8.2.1 Standoff Height

As illustrated in Figure 8-1, the standoff height specification for this device (between 0.050 mm and 0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest point on the package body. Due to warpage, the lowest point on the package body is located in the center of the package at the exposed thermal pad.

Using this definition of standoff height provides the correct result for determining the correct solder paste thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (SLMA002), the recommended range of solder paste thickness for this package is between 0.152 mm and 0.178 mm.

Figure 8-1 Standoff Height Measurement on 176-pin PTP Package

8.2.2 PowerPAD™ PCB Footprint

In general, for proper thermal performance, the thermal pad under the package body should be as large as possible. However, the soldermask opening for the PowerPAD™ should be sized to match the pad size on the 176-pin PTP package; as illustrated in Figure 8-2.

Figure 8-2 Soldermask Opening Should Match Size of Package Thermal Pad

8.3 Packaging Information

The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document.