ZHCS596B December 2011 – June 2019 AFE030
PRODUCTION DATA.
The AFE030 is controlled through a serial interface that allows read/write access to the control and data registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid host SPI communications protocol. Table 10 through Table 19 show the complete register information.
| REGISTER | ADDRESS | DEFAULT | FUNCTION |
|---|---|---|---|
| ENABLE1 | 01h | 00h | Block enable or disable |
| GAIN SELECT | 02h | 32h | Rx and Tx gain select |
| ENABLE2 | 03h | 00h | Block enable or disable |
| CONTROL1 | 04h | 00h | Frequency select and calibration, Tx and Rx status |
| CONTROL2 | 05h | 01h | Interrupt enable |
| RESET | 09h | 00h | Interrupt status and device reset |
| DIE_ID | 0Ah | 01h | Die name |
| REVISION | 0Bh | 02h | Die revision |
| BIT NAME | LOCATION
(15 = MSB) |
R/W | FUNCTION |
|---|---|---|---|
| ADDR8 | 8 | W | Register address bit |
| ADDR9 | 9 | W | Register address bit |
| ADDR10 | 10 | W | Register address bit |
| ADDR11 | 11 | W | Register address bit |
| ADDR12 | 12 | W | Register address bit |
| ADDR13 | 13 | W | Register address bit |
| ADDR14 | 14 | W | Register address bit |
| R/W | 15 | W | Read/write: read = 1, write = 0 |
| Enable1 Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| PA | 0 | 0 | R/W | This bit is used to enable/disable the PA block.
0 = Disabled 1 = Enabled |
| TX | 1 | 0 | R/W | This bit is used to enable/disable the Tx block.
0 = Disabled 1 = Enabled |
| RX | 2 | 0 | R/W | This bit is used to enable/disable the Rx block.
0 = Disabled 1 = Enabled |
| ERX | 3 | 0 | R/W | This bit is used to enable/disable the ERx block.
0 = Disabled 1 = Enabled |
| ETX | 4 | 0 | R/W | This bit is used to enable/disable the ETx block.
0 = Disabled 1 = Enabled |
| DAC | 5 | 0 | R/W | This bit is used to enable/disable the DAC block.
0 = DAC disabled; switch is connected to Tx_PGA_IN pin. 1 = DAC enabled; switch is connected to DAC output. |
| — | 6 | 0 | — | Reserved |
| — | 7 | 0 | — | Reserved |
| Gain Select Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| RX1G-0,
RX1G-1 |
0, 1 | 0, 1 | R/W | This bit is used to set the gain of the Rx PGA1.
00 = 0.25 V/V 01 = 0.5 V/V 10 = 1 V/V 11 = 2 V/V |
| RX2G-0,
RX2G-1 |
2, 3 | 0, 0 | R/W | This bit is used to set the gain of the Rx PGA2.
00 = 1 V/V 01 = 4 V/V 10 = 16 V/V 11 = 64 V/V |
| TXG-0,
TXG-1 |
4, 5 | 1, 1 | R/W | This bit is used to set the gain of the Tx PGA.
00 = 0.25 V/V 01 = 0.5 V/V 10 = 0.707 V/V 11 = 1 V/V |
| — | 6 | 0 | — | Reserved |
| — | 7 | 0 | — | Reserved |
| Enable2 Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| ZC | 0 | 0 | R/W | This bit is used to enable/disable the ZC block.
0 = Disabled 1 = Enabled |
| REF1 | 1 | 0 | R/W | This bit is used to enable/disable the REF1 block.
0 = Disabled 1 = Enabled |
| REF2 | 2 | 0 | R/W | This bit is used to enable/disable the REF2 block.
0 = Disabled 1 = Enabled |
| PA_OUT | 3 | 0 | R/W | This bit is used to enable/disable the PA output stage.
When the PA output stage is enabled it functions normally with a low output impedance, capable of driving heavy loads. When the PA output stage is disabled it is placed into a high impedance state. 0 = Disabled 1 = Enabled |
| — | 4 | 0 | — | Reserved |
| — | 5 | 0 | — | Reserved |
| — | 6 | 0 | — | Reserved |
| — | 7 | 0 | — | Reserved |
| Control2 Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| — | 0 | 0 | — | Reserved |
| — | 1 | 0 | — | Reserved |
| — | 2 | 0 | — | Reserved |
| — | 3 | 0 | — | Reserved |
| — | 4 | 0 | — | Reserved |
| T_FLAG_EN | 5 | 0 | R/W | This bit is used to enable/disable the T_flag bit in the RESET Register.
0 = Disabled 1 = Enabled |
| I_FLAG_EN | 6 | 0 | R/W | This bit is used to enable/disable the I_flag bit in the RESET Register.
0 = Disabled 1 = Enabled |
| — | 7 | X | — | Reserved |
| Reset Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| -- | 0 | 0 | -- | Reserved |
| -- | 1 | 0 | -- | Reserved |
| SOFTRST0,
SOFTRST1, SOFTRST2 |
2, 3, 4 | 0, 0, 0 | W | These bits are used to perform a software reset of the ENABLE1, ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT registers. Writing '101' to these registers performs a software reset. |
| T_FLAG | 5 | 0 | R/W | This bit is used to indicate the status of a PA thermal overload.
0 = On read, indicates that no thermal overload has occurred since the last reset. 0 = On write, resets this bit. 1 = On read, indicates that a thermal overload has occurred since the last reset. Remains latched until reset. |
| I_FLAG | 6 | 0 | R/W | This bit is used to indicate the status of a PA output current overload.
0 = On read indicates that no current overload has occurred since the last reset. 0 = On write, resets this bit. 1 = On read indicates that a current overload has occurred since the last reset. Remains latched until reset. |
| — | 7 | 0 | — | Reserved |
| DieID Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| DIE ID<0> | 0 | 1 | R | The DieID Register is hard-wired. |
| DIE ID<1> | 1 | 0 | R | The DieID Register is hard-wired. |
| DIE ID<2> | 2 | 0 | R | The DieID Register is hard-wired. |
| DIE ID<3> | 3 | 0 | R | The DieID Register is hard-wired. |
| DIE ID<4> | 4 | 0 | R | The DieID Register is hard-wired. |
| DIE ID<5> | 5 | 0 | R | The DieID Register is hard-wired. |
| DIE ID<6> | 6 | 0 | R | The DieID Register is hard-wired. |
| DIE ID<7> | 7 | 0 | R | The DieID Register is hard-wired. |
| Revision Register <7:0> | ||||
|---|---|---|---|---|
| BIT NAME | LOCATION
(0 = LSB) |
DEFAULT | R/W | FUNCTION |
| REVISION ID<0> | 0 | 0 | R | The Revision Register is hard-wired. |
| REVISION ID<1> | 1 | 1 | R | The Revision Register is hard-wired. |
| REVISION ID<2> | 2 | 0 | R | The Revision Register is hard-wired. |
| REVISION ID<3> | 3 | 0 | R | The Revision Register is hard-wired. |
| REVISION ID<4> | 4 | 0 | R | The Revision Register is hard-wired. |
| REVISION ID<5> | 5 | 0 | R | The Revision Register is hard-wired. |
| REVISION ID<6> | 6 | 0 | R | The Revision Register is hard-wired. |
| REVISION ID<7> | 7 | 0 | R | The Revision Register is hard-wired. |