The output bit mapper allows to change the output bit order for any selected interface mode.

It is a two step process to change the output bit mapping and assemble the output data bus:

1. Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier bit as shown in the Table 8-8. The MSB starts with bit D19 – depending on output resolution chosen the LSB would be D6 (14-bit) to D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap the serial output format.

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address 0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode both the current and the previous sample have to be used in the address space as shown in Figure 8-39. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

In the following example (Figure 8-40), the 16-bit 2-wire serial output is reordered to where lane DA5/DB5 carries the 8 MSB and lane DA6/DB6 carries 8 LSBs.

1-wire mode: Only the ‘current’ sample needs to programmed in the address space. If desired, it can be duplicated on DA5/DB5 as well (using addresses shown in Figure 8-41 in order to have a redundant output. Lane DA5/DB5 needs to be powered up in that case.

?-wire mode: The output is only on lane DA6 and the sample order is programmed into the 40 addresses of chA (from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown in Figure 8-42.