ZHCSQN6 May 2022 ADC3644
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications
- 6.8 Timing Requirements
- 6.9 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application Information Disclaimer
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.2 Initialization Set Up
After power-up, the internal registers must be initialized to the default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 9-5.
- Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap reference will power up and settle out in ~ 2ms.
- Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
- Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock cycles.
- Begin programming using SPI interface.
Figure 9-5 Initialization of serial registers after power upTable 9-5 Power-up timing
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| t1 | Power-on delay: delay from power up to logic level of REFBUF pin | 2 | ms | ||
| t2 | Delay from REFBUF pin logic level to RESET rising edge | 100 | ns | ||
| t3 | RESET pulse width | 1 | us | ||
| t4 | Delay from RESET disable to SEN active | ~ 200000 | clock cycles | ||