ZHCSE80B July 2014 – April 2017 ADC3441 , ADC3442 , ADC3443 , ADC3444
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics: General
- 7.6 Electrical Characteristics: ADC3441, ADC3442
- 7.7 Electrical Characteristics: ADC3443, ADC3444
- 7.8 AC Performance: ADC3441
- 7.9 AC Performance: ADC3442
- 7.10 AC Performance: ADC3443
- 7.11 AC Performance: ADC3444
- 7.12 Digital Characteristics
- 7.13 Timing Requirements: General
- 7.14 Timing Requirements: LVDS Output
- 7.15 Typical Characteristics: ADC3441
- 7.16 Typical Characteristics: ADC3442
- 7.17 Typical Characteristics: ADC3443
- 7.18 Typical Characteristics: ADC3444
- 7.19 Typical Characteristics: Common
- 7.20 Typical Characteristics: Contour
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6
Register Maps
- 9.6.1
Serial Register Description
- 9.6.1.1 Register 01h (address = 01h)
- 9.6.1.2 Register 03h (address = 03h)
- 9.6.1.3 Register 04h (address = 04h)
- 9.6.1.4 Register 05h (address = 05h)
- 9.6.1.5 Register 06h (address = 06h)
- 9.6.1.6 Register 07h (address = 07h)
- 9.6.1.7 Register 09h (address = 09h)
- 9.6.1.8 Register 0Ah (address = 0Ah)
- 9.6.1.9 Register 0Bh (address = 0Bh)
- 9.6.1.10 Register 13h (address = 13h)
- 9.6.1.11 Register 0Eh (address = 0Eh)
- 9.6.1.12 Register 0Fh (address = 0Fh)
- 9.6.1.13 Register 15h (address = 15h)
- 9.6.1.14 Register 25h (address = 25h)
- 9.6.1.15 Register 27h (address = 27h)
- 9.6.1.16 Register 11Dh (address = 11Dh)
- 9.6.1.17 Register 122h (address = 122h)
- 9.6.1.18 Register 134h (address = 134h)
- 9.6.1.19 Register 139h (address = 139h)
- 9.6.1.20 Register 21Dh (address = 21Dh)
- 9.6.1.21 Register 222h (address = 222h)
- 9.6.1.22 Register 234h (address = 234h)
- 9.6.1.23 Register 239h (address = 239h)
- 9.6.1.24 Register 308h (address = 308h)
- 9.6.1.25 Register 41Dh (address = 41Dh)
- 9.6.1.26 Register 422h (address = 422h)
- 9.6.1.27 Register 434h (address = 434h)
- 9.6.1.28 Register 439h (address = 439h)
- 9.6.1.29 Register 51Dh (address = 51Dh)
- 9.6.1.30 Register 522h (address = 522h)
- 9.6.1.31 Register 534h (address = 534h)
- 9.6.1.32 Register 539h (address = 539h)
- 9.6.1.33 Register 608h (address = 608h)
- 9.6.1.34 Register 70Ah (address = 70Ah)
- 9.6.1
Serial Register Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTQ|56
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTQ|56
訂購信息
12 Layout
12.1 Layout Guidelines
The ADC344x EVM layout may be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 203. Some important points to remember during laying out the board are:
- Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions, as shown in the reference layout of Figure 203 as much as possible.
- In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 203 as much as possible.
- Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital output traces must not be kept parallel to the analog input traces because this configuration may result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched in length to avoid skew among outputs.
- At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors may be kept close to the supply source.
12.2 Layout Example
Figure 203. Typical Layout of the ADC344x Board