9.1.1 Start-Up Sequence

The steps in Table 143 are recommended as the power-up sequence when the ADC32RF82 is in the decimation-by-4 complex output mode.

9.1.2 Hardware Reset

Figure 264 and Table 144 show the timing information for the hardware reset.

Figure 264. Hardware Reset Timing Diagram

9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 5: quantization noise, thermal noise, and jitter. The quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

Equation 5.

Equation 6 calculates the SNR limitation resulting from sample clock jitter:

Equation 6.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (90 f_S) is set by the noise of the clock input buffer and the external clock jitter. Equation 7 calculates T_Jitter:

Equation 7.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADC32RF82 has a thermal noise of approximately 63 dBFS and an internal aperture jitter of 90 f_S. The SNR, is shown in Figure 265, depending on the amount of external jitter for different input frequencies.

Figure 265. ADC SNR vs Input Frequency and External Clock Jitter

9.1.3.1 External Clock Phase Noise Consideration

External clock jitter can be calculated as shown in Figure 266 by integrating the phase noise of the clock source out to approximately two times of the ADC sampling rate (2 × f_S). In order to maximize the ADC SNR, an external band-pass filter is recommended to be used on the clock input. This filter reduces the jitter contribution from the broadband clock phase noise floor by effectively reducing the integration bandwidth to the pass band of the band-pass filter. This method is suitable when estimating the overall ADC SNR resulting from clock jitter at a certain input frequency.

Figure 266. Integration Bandwidth for Extracting Jitter from Clock Phase Noise

However, when estimating the affect of a nearby blocker (such as a strong in-band interferer to the sensitivity, the phase noise information shown in Figure 267 can be used directly to estimate the noise budget contribution at a certain offset frequency.

Figure 267. Small Wanted Signal in Presence of Interferer

At the sampling instant, the phase noise profile of the clock source convolves with the input signal (for example, the small wanted signal and the strong interferer merge together). If the power of the clock phase noise in the signal band of interest is too large, the wanted signal cannot not be recovered.

The resulting equivalent phase noise at the ADC input is also dependent on the sampling rate of the ADC and frequency of the input signal. Equation 8 shows the ADC sampling rate scales the clock phase noise.

Equation 8.

Using this information, the noise contribution resulting from the phase noise profile of the ADC sampling clock can be calculated.

9.1.4 Power Consumption in Different Modes

The ADC32RF82 consumes approximately 6 W of power when both channels are active with a divide-by-4 complex output. When different DDC options are used, the power consumption on the DVDD supply changes by a small amount but remains unaffected on other supplies. In the applications requiring just one channel to be active, channel A must be chosen as the active channel and channel B can be powered down. Power consumption reduces to approximately 4 W in single-channel operation with a divide-by-3.4 option at a 2457.6-MSPS device clock rate.

Table 145, Table 146, and Table 147 show power consumption in different DDC modes for dual-channel and single-channel operation.

9.1.5 Using DC Coupling in the ADC32RF82

The ADC32RF82 can be used in dc-coupling applications. However, the following points must be considered when designing the system:

1. Ensure that the correct common-mode voltage is used at the ADC analog inputs.

The analog inputs are internally self-biased to V_CM through approximately a 33-Ω resistor. The internal biasing resistors also function as a termination resistor. However, if a different termination is required, the external resistor R_TERM can be differentially placed between the analog inputs, as shown in Figure 268. The amplifier V_OCM pin is recommended to be driven from the CM pin of the ADC to help the amplifier output common-mode voltage track the required common-mode voltage of the ADC.


1. Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω.
2. R_DC is approximately 65 Ω.
Figure 268. The ADC32RF82 in a DC-Coupling Application
2. Ensure that the correct SPI settings are written to the ADC.

As shown in Figure 269, the ADC32RF82 has a digital block that estimates and corrects the offset mismatch among four interleaving ADC cores for a given channel.

Figure 269. Offset Corrector in the ADC32RF82

The offset corrector block nullifies dc, f_S / 8, f_S / 4, 3 f_S / 8, and f_S / 2. The resulting spectrum becomes free from static spurs at these frequencies. The corrector continuously processes the data coming from the interleaving ADC cores and cannot distinguish if the tone at these frequencies is part of signal or if the tone originated from a mismatch among the interleaving ADC cores. Thus, in applications where the signal is present at these frequencies, the offset corrector block can be bypassed.

9.1.5.1 Bypassing the Offset Corrector Block

When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector is frozen so that the last estimated value is held. Required register writes are provided in Table 148.

Table 148. Freezing and Bypassing the Offset Corrector Block

STEP	REGISTER WRITE	COMMENT
STEPS FOR FREEZING THE CORRECTOR BLOCK
1	—	Signal source is turned off. The device detects an idle channel at its input.
2	—	Wait for at least 0.4 ms for the corrector to estimate the internal offset
3	Address 4001h, value 00h	Select Offset Corr Page Channel A
	Address 4002h, value 00h
	Address 4003h, value 00h
	Address 4004h, value 61h
	Address 6068h, value C2h	Freeze the corrector for channel A
	Address 4003h, value 01h	Select Offset Corr Page Channel B
	Address 6068h, value C2h	Freeze the corrector for channel B
4	—	Signal source can now be turned on
STEPS FOR BYPASSING THE CORRECTOR BLOCK
1	Address 4001h, value 00h	—
	Address 4002h, value 00h
	Address 4003h, value 00h
	Address 4004h, value 61h	Select Offset Corr Page Channel A
	Address 6068h, value 46h	Disable the corrector for channel A
	Address 4003h, value 01h	Select Offset Corr Page Channel B
	Address 6068h, value 46h	Disable the corrector for channel B

9.1.5.1.1 Effect of Temperature

Figure 270 and Figure 271 show the behavior of nf_S / 8 tones with respect to temperature when the offset corrector block is frozen or disabled.

Figure 270. Offset Corrector Block Frozen at Room Temperature

Figure 271. Offset Corrector Block Disabled

9.2.1 Design Requirements

By using the simple drive circuit of Figure 273, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

Figure 273. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 273.

9.2.3 Application Curves

Figure 274 and Figure 275 show the typical performance at 100 MHz and 1850 MHz, respectively.

SNR = 62,4 dBFS; SFDR = 71 dBc; HD2 = –71 dBc; HD3 = –83 dBc; non HD2, HD3 = 82 dBc; IL spur = 80 dBc; fIN = 100 MHz

Figure 274. FFT for 100-MHz Input Frequency

SNR = 58 dBFS; SFDR = 69 dBc; HD2 = –69 dBc; HD3 = –75 dBc; non HD2, HD3 = 74 dBc; IL spur = 78 dBc; fIN = 1850 MHz

Figure 275. FFT for 1850-MHz Input Frequency