ZHCSD67C July 2014 – March 2016 ADC3241 , ADC3242 , ADC3243 , ADC3244
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics: ADC3241, ADC3242
- 7.6 Electrical Characteristics: ADC3243, ADC3244
- 7.7 Electrical Characteristics: General
- 7.8 AC Performance: ADC3241
- 7.9 AC Performance: ADC3242
- 7.10 AC Performance: ADC3243
- 7.11 AC Performance: ADC3244
- 7.12 Digital Characteristics
- 7.13 Timing Requirements: General
- 7.14 Timing Requirements: LVDS Output
- 7.15 Typical Characteristics: ADC3241
- 7.16 Typical Characteristics: ADC3242
- 7.17 Typical Characteristics: ADC3243
- 7.18 Typical Characteristics: ADC3244
- 7.19 Typical Characteristics: Common
- 7.20 Typical Characteristics: Contour
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6
Register Maps
- 9.6.1 Summary of Special Mode Registers
- 9.6.2
Serial Register Description
- 9.6.2.1 Register 01h
- 9.6.2.2 Register 03h
- 9.6.2.3 Register 04h
- 9.6.2.4 Register 05h
- 9.6.2.5 Register 06h
- 9.6.2.6 Register 07h
- 9.6.2.7 Register 09h
- 9.6.2.8 Register 0Ah
- 9.6.2.9 Register 0Bh
- 9.6.2.10 Register 0Eh
- 9.6.2.11 Register 0Fh
- 9.6.2.12 Register 13h (address = 13h)
- 9.6.2.13 Register 15h
- 9.6.2.14 Register 25h
- 9.6.2.15 Register 27h
- 9.6.2.16 Register 41Dh
- 9.6.2.17 Register 422h
- 9.6.2.18 Register 434h
- 9.6.2.19 Register 439h
- 9.6.2.20 Register 51Dh
- 9.6.2.21 Register 522h
- 9.6.2.22 Register 534h
- 9.6.2.23 Register 539h
- 9.6.2.24 Register 608h
- 9.6.2.25 Register 70Ah
- 10Applications and Implementation
- 11Power-Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購(gòu)信息
10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical applications involving transformer coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 176 and Figure 177 show the impedance (Zin = Rin || Cin) across the ADC input pins.
Figure 176. Differential Input Resistance (RIN)
Figure 177. Differential Input Capacitance (CIN)
10.2 Typical Applications
10.2.1 Driving Circuit Design: Low Input Frequencies
Figure 178. Driving Circuit for Low Input Frequencies
10.2.1.1 Design Requirements
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.
10.2.1.2 Detailed Design Procedure
A typical application involving using two back-to-back coupled transformers is shown in Figure 178. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches.
10.2.1.3 Application Curve
Figure 179 shows the performance obtained by using circuit shown in Figure 178.
| SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc |
10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
Figure 180. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)
10.2.2.1 Design Requirements
See the Design Requirements section for further details.
10.2.2.2 Detailed Design Procedure
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 180.
10.2.2.3 Application Curve
Figure 181 shows the performance obtained by using circuit shown in Figure 180.
| SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS, THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc |
10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
Figure 182. Driving Circuit for High input Frequencies ( fIN > 230 MHz)
10.2.3.1 Design Requirements
See the Design Requirements section for further details.
10.2.3.2 Detailed Design Procedure
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 182.
10.2.3.3 Application Curve
Figure 183 shows the performance obtained by using circuit shown in Figure 182.
| SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS, THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc |