The ADC322x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 9-9. Some important points to remember during laying out the board are:
- Analog inputs are located on opposite sides of
the device pin out to make sure minimum crosstalk on the package level. To
minimize crosstalk onboard, the analog inputs must exit the pin out in opposite
directions, as shown in the reference layout of Figure 9-9 as much as possible.
- In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 9-9 as much as possible.
- Keep digital outputs away from analog inputs. When these digital outputs exit the pin out, the digital output traces must not be kept parallel to the analog input traces because this configuration can result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver (such as an FPGA or an ASIC) must be matched in length to avoid skew among outputs.
- At each power-supply pin (AVDD and DVDD), a 0.1-μF decoupling capacitor must be kept close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-μF, 1-μF, and
0.1-μF capacitors can be kept close to the supply source.