ZHCSP07A October 2021 – October 2024 ADC12DJ800 , ADC12QJ800 , ADC12SJ800
PRODUCTION DATA
Background calibration mode allows the ADC to continuously operate, with no interruption of data. This continuous operation is accomplished by activating extra ADC cores that are calibrated to take over operation for one of the other previously active ADC cores. For the quad channel device, ADC cores 0 and 1 share one extra ADC core (ADC core 2) and ADC cores 4 and 5 share the other extra ADC core (ADC core 3). For the dual channel device, ADC cores 0 and 1 share one extra ADC core (ADC core 2). For the single channel device, ADC core 0 has one extra ADC core (ADC core 2). When an ADC core is taken off-line the ADC is then calibrated and then can in turn take over to allow the next ADC to be calibrated. This process operates continuously, ensuring the ADC cores always provide the optimum performance regardless of system operating condition changes. Only one of the cores is calibrated at a time to reduce power consumption, however the additional active ADC core does increase the power consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power consumption in comparison with the standard background calibration mode. Background calibration can be enabled by setting CAL_BG. CAL_TRIG_EN must be set to 0 and CAL_SOFT_TRIG must be set to 1.
Great care has been taken to minimize effects on converted data as the core switching process occurs, however, small brief glitches may still occur on the converter data as the cores are swapped. It is recommended to set register ADC_SRC_DLY (address = 0x9A) to 0x1F and MUX_SEL_DLY (address = 0x9B) to 0x1E.
See the Typical Characteristics section for examples of possible glitches in sine-wave and DC signals.