ZHCSP07A October 2021 – October 2024 ADC12DJ800 , ADC12QJ800 , ADC12SJ800
PRODUCTION DATA
JMODEs that use four or less lanes allow the use of redundancy on the JESD204C output. For instance, a system may have two FPGAs or ASICs connected to a single device, if the FPGA or ASIC is deemed the weak point in system reliability. In this example system, only one FPGA or ASIC operates at a time with the redundant FPGA or ASIC only being enabled if a fault is detected in the default FPGA or ASIC. To use this mode, the lower four SerDes lanes (D3-D0) must be routed to a single FPGA or ASIC and the upper four SerDes lanes (D7-D4) routed to the redundant FPGA or ASIC. The lower four lanes are the "default" lanes and the upper four lanes are the "alternate" lanes. The desired lanes are chosen by setting ALT_LANES parameter to 0 for the default lanes or 1 for the alternate lanes. Only one set of SerDes outputs can be operated at a time.