ZHCSON7A July 2021 – October 2024 ADC12DJ800-Q1 , ADC12QJ800-Q1 , ADC12SJ800-Q1
PRODUCTION DATA
The input offset voltage for each analog input of the quad channel device can be adjusted through the OFSxy registers, where x represents the ADC core (0, 1, 2, 3, 4 or 5) and y represents the analog input for ADC core 2 (A or B) and core 3 (C or D). The y parameter is omitted for ADC core 0, 1, 4 and 5 since these cores always sample the same analog input. For the dual channel device, x represents the ADC core (0, 1, or 2) and y represents the analog input for ADC core 2 (A or B). The y parameter is omitted for ADC core 0 and 1 since these cores always sample the same analog input. For the single channel device, x represents the ADC core (0 or 2) and the y parameter is omitted for ADC core 0 since this core always samples the same analog input. The adjustment range is approximately 33 mV to –33 mV differential. See the Calibration Modes and Trimming section for more information.