ZHCSOS8A October 2021 – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics: DC Specifications
- 5.6 Electrical Characteristics: Power Consumption
- 5.7 Electrical Characteristics: AC Specifications
- 5.8 Timing Requirements
- 5.9 Switching Characteristics
- 5.10 Typical Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Device Comparison
- 6.3.2 Analog Input
- 6.3.3 ADC Core
- 6.3.4
Clocking
- 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
- 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
- 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
- 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
- 6.3.4.5
JESD204C Interface
- 6.3.4.5.1 Transport Layer
- 6.3.4.5.2 Scrambler
- 6.3.4.5.3 Link Layer
- 6.3.4.5.4 8B/10B Link Layer
- 6.3.4.5.5 64B/66B Link Layer
- 6.3.4.5.6 Physical Layer
- 6.3.4.5.7 JESD204C Enable
- 6.3.4.5.8 Multi-Device Synchronization and Deterministic Latency
- 6.3.4.5.9 Operation in Subclass 0 Systems
- 6.3.4.5.10 Alarm Monitoring
- 6.4
Device Functional Modes
- 6.4.1 Low Power Mode and High Performance Mode
- 6.4.2 JESD204C Modes
- 6.4.3 Power-Down Modes
- 6.4.4
Test Modes
- 6.4.4.1 Serializer Test-Mode Details
- 6.4.4.2 PRBS Test Modes
- 6.4.4.3 Clock Pattern Mode
- 6.4.4.4 Ramp Test Mode
- 6.4.4.5 Short and Long Transport Test Mode
- 6.4.4.6 D21.5 Test Mode
- 6.4.4.7 K28.5 Test Mode
- 6.4.4.8 Repeated ILA Test Mode
- 6.4.4.9 Modified RPAT Test Mode
- 6.4.4.10 Calibration Modes and Trimming
- 6.4.4.11 Offset Calibration
- 6.4.4.12 Trimming
- 6.5 Programming
- 6.6 SPI_Register_Map Registers
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- AAV|144
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
6.5.6 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifics the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming transaction. ASCEND controls whether the address value ascends (increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit. Figure 6-19 shows the streaming mode transaction details.
Figure 6-19 Serial
Interface Protocol: Streaming Read/WriteSee the SPI_Register_Map Registers section for detailed information regarding the registers
The serial interface must not be accessed during ADC calibration. Accessing the serial interface during this time impairs the performance of the device until the device is calibrated correctly. Writing or reading the serial registers also reduces dynamic ADC performance for the duration of the register access times.