SN74AUP1G58
- Available in the Texas Instruments NanoStar? Packages
- Low Static-Power Consumption
(ICC = 0.9 μA Max) - Low Dynamic-Power Consumption
(Cpd = 4.6 pF Typ at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typ)
- Low Noise – Overshoot and Undershoot <10% of VCC
- Ioff Supports Partial-Power-Down Mode Operation
- Includes Schmitt-Trigger Inputs
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.5 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
NanoStar is a trademark of Texas Instruments
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity, which produces very low undershoot and overshoot characteristics.
The SN74AUP1G58 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and better switching noise immunity at the input.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
您可能感興趣的相似產(chǎn)品
功能與比較器件相同,且具有相同引腳
技術(shù)文檔
| 類型 | 標(biāo)題 | 下載最新的英語(yǔ)版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | SN74AUP1G58 Low-Power Configurable Multiple-Function Gate 數(shù)據(jù)表 (Rev. J) | 2010年 3月 29日 | |||
| 應(yīng)用簡(jiǎn)報(bào) | 了解施密特觸發(fā)器 (Rev. B) | PDF | HTML | 英語(yǔ)版 (Rev.B) | PDF | HTML | 2025年 5月 5日 | |
| 應(yīng)用簡(jiǎn)報(bào) | 在系統(tǒng)設(shè)計(jì)中使用可配置邏輯 | PDF | HTML | 英語(yǔ)版 | PDF | HTML | 2024年 11月 19日 | |
| 選擇指南 | Little Logic Guide 2018 (Rev. G) | 2018年 7月 6日 | ||||
| 選擇指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
| 應(yīng)用手冊(cè) | How to Select Little Logic (Rev. A) | 2016年 7月 26日 | ||||
| 選擇指南 | 邏輯器件指南 2014 (Rev. AA) | 最新英語(yǔ)版本 (Rev.AC) | PDF | HTML | 2014年 11月 17日 | ||
| 選擇指南 | 小尺寸邏輯器件指南 (Rev. E) | 最新英語(yǔ)版本 (Rev.G) | 2012年 7月 16日 | |||
| 應(yīng)用手冊(cè) | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
| 選擇指南 | Logic Guide (Rev. AC) | PDF | HTML | 1994年 6月 1日 |
設(shè)計(jì)和開發(fā)
如需其他信息或資源,請(qǐng)點(diǎn)擊以下任一標(biāo)題進(jìn)入詳情頁(yè)面查看(如有)。
5-8-LOGIC-EVM — 支持 5 至 8 引腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評(píng)估模塊
| 封裝 | 引腳 | CAD 符號(hào)、封裝和 3D 模型 |
|---|---|---|
| DSBGA (YFP) | 6 | Ultra Librarian |
| DSBGA (YZP) | 6 | Ultra Librarian |
| SOT-23 (DBV) | 6 | Ultra Librarian |
| SOT-5X3 (DRL) | 6 | Ultra Librarian |
| SOT-SC70 (DCK) | 6 | Ultra Librarian |
| USON (DRY) | 6 | Ultra Librarian |
| X2SON (DSF) | 6 | Ultra Librarian |
訂購(gòu)和質(zhì)量
- RoHS
- REACH
- 器件標(biāo)識(shí)
- 引腳鍍層/焊球材料
- MSL 等級(jí)/回流焊峰值溫度
- MTBF/時(shí)基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測(cè)
- 制造廠地點(diǎn)
- 封裝廠地點(diǎn)