RF receivers
Meet your performance, bandwidth and power requirements with high integration wideband receivers
High channel density, wide signal bandwidth and high resolution integrated data converters enable better dynamic range and lower bill of materials in the most demanding wireless, defense and test receiver applications.
Browse by category
Related categories
Design & development resources
Firmware
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Evaluation board
ADC32RF55 evaluation module for dual-channel 14-bit 3GSPS RF-sampling ADC with low NSD
The ADC32RF55 evaluation module (EVM) is designed to evaluate the ADC32RF55 family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC32RF55, a 14-bit, dual-channel 3GSPS ADC with JESD204B interface and allows for evaluation of all sample rates devices in the family.
Evaluation board
ADC12DJ5200RF RF-sampling 12-bit dual 5.2GSPS or single 10.4GSPS ADC evaluation module
The ADC12DJ5200RF evaluation module (EVM) is designed to evaluate the ADC12DJ5200RF family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ5200RF, a 12-bit, dual-channel 5.2GSPS or single-channel 10.4GSPS ADC with JESD204B interface and allows for evaluation (...)
Technical resources
Technical article
Keys to quick success using high-speed data converters
Learn how TI makes it easy to evaluate high speed data converters and AFEs?
Video series
High-speed signal chain training series
Online training series covering topics such as RF-sampling, JESD204B and more.?
Video series
High-speed data converter fundamentals
These videos cover the fundamentals of high-speed data converters, including an overview of the architectures of both ADCs and DACs.