SNVSA89A December 2014 – May 2015 UCC27528-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
1 Features
- Qualified for Automotive Applications
- AEC-Q100 Device Temperature Grade 1
- Industry-Standard Pin Out
- Two Independent Gate-Drive Channels
- 5-A Peak Source and Sink Drive Current
- CMOS Input Logic Threshold
(Function of Supply Voltage on VDD Pins) - Hysteretic Logic Thresholds for High Noise Immunity
- Independent Enable Function for Each Output
- Inputs and Enable Pin Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage
- 4.5-V to 18-V Single Supply Range
- Outputs Held Low During VDD UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
- Fast Propagation Delays (17-ns Typical)
- Fast Rise and Fall Times (7-ns and 6-ns Typical)
- 1-ns Typical Delay Matching Between 2 Channels
- Outputs Held in Low When Inputs Floating
- SOIC-8 Package
- Operating Temperature Range of –40°C to 140°C
- –5-V Negative Voltage Handling Capability on Input Pins
2 Applications
- Automotive
- Switch-Mode Power Supplies
- DC-to-DC Converters
- Motor Control, Solar Power
- Gate Drive for Emerging Wideband Gap Power Devices Such as GaN
3 Description
The UCC27528-Q1 device is a dual-channel, high-speed, low-side gate driver capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27528-Q1 device can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay of 17 ns (typical). In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. The input pin thresholds are based on CMOS logic, which is a function of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. The enable pins are based on TTL and CMOS compatible logic, independent of the VDD supply voltage.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| UCC27528-Q1 | SOIC (8) | 4.90 mm × 3.91 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
Dual Non-Inverting Inputs
